EM78P257AP datasheet(29/91 Pages) EMC

29 / 91 page

EM78P257

OTP ROM

This specification is subject to change without prior notice.

07.27.2004 (V1.4)

enabled) will cause the device to reset. The WDT can be enabled or disabled at any time during the normal mode

by software programming. Refer to WDTE bit of IOCE0 register. With no prescaler, the WDT time-out period is

approximately 18 ms

1 or 1ms2 (one oscillator start-up timer period).

8-Bit counter

WDT

Prescaler

8 to 1 MUX

WDT Time out

WDTE

(IOCE0)

TCC Pin

MUX

CLK (Fosc/2 or Fosc/4)

8-Bit Counter (RC)

8 to 1 MUX

TE (CONT)

Data Bus

TCC overflow

interrupt

TS (CONT)

SYNC

2 cycles

TCC (R1)

PSW2~0

(IOCE0)

Prescaler

PSR2~0

(CONT)

Fig. 6 Block Diagram of TCC and WDT

4.4 I/O Ports

The I/O registers, (Port 5, Port 6, and Port 7), are bi-directional tri-state I/O ports. Port 5 is pulled-high internally by

software. Likewise, P6 has its open-drain output also through software. Port 5 features an input status changed

interrupt (or wake-up) function and is pulled-down by software. Each I/O pin can be defined as "input" or "output" pin

by the I/O control register (IOC5 ~ IOC7). The I/O registers and I/O control registers are both readable and writable.

The I/O interface circuits for Port 5, Port 6 and Port7 are shown in Fig. 7, Fig. 8, and Fig. 9 respectively.

1 NOTE:

VDD=5V, Setup time period = 15.4ms ± 30%.

VDD=3V, Setup time period = 17.6ms ± 30%.

2 NOTE:

VDD=5V, Setup time period = 1.07ms ± 30%.

VDD=3V, Setup time period = 1.22ms ± 30%.

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