MP8759 – 26V, 8A, SYNCHRONOUS, STEP-DOWN CONVERTER

MP8759 Rev. 1.1

www.MonolithicPower.com

17

4/13/2017

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Selecting the Output Capacitor

The output capacitor is required to maintain the

DC output voltage. Ceramic or POS capacitors

are recommended. The output voltage ripple can

be estimated with Equation (14):

OUT

OUT

OUT

ESR

SW

IN

SW

OUT

VV

1

V(1

) (R

)

FL

V

8 F

C



 









(14)

With ceramic capacitors, the impedance at the

switching frequency is dominated by the

capacitance. The output voltage ripple is mainly

caused by the capacitance. For simplification, the

output voltage ripple can be estimated with

Equation (15):

OUT

OUT

OUT

2

SW

OUT

IN

VV

V(1

)

8F

L C

V



 

 

(15)

In the case of POS capacitors, the ESR

dominates the impedance at the switching

frequency.

The

output

ripple

can

be

approximated with Equation (16):

OUT

OUT

OUT

ESR

SW

IN

VV

V(1

) R

FL

V



 





(16)

The maximum output capacitor limitation should

be also considered during the design application.

If the output capacitor value is too high, the

output voltage cannot reach the design value

during the soft-start time and fails to regulate.

can be limited approximately with Equation (17):

O_ MAX

LIM _ AVG

OUT

ss

OUT

C(I

I

) T / V





(17)

time. The inductance value can be calculated

with Equation (18):

OUT

OUT

SW

L

IN

VV

L(1

)

FI

V

 



(18)

current.

The inductor should not saturate under the

maximum inductor peak current, including short

12A.

PCB Layout Guidelines

Efficient PBC layout is critical for stable operation.

A four-layer layout is strongly recommended to

achieve better thermal performance. For best

results, refer to Figure 10 and follow the

guidelines below.

1. Place the high current paths (GND, IN, and

SW) very close to the device with short, direct,

and wide traces.

2. Place the input capacitors as close to IN and

GND as possible.

3. Place the decoupling capacitor as close to

VCC and GND as possible.

4. Keep the switching node SW short and away

from the feedback network.

5. Keep the BST voltage path as short as

possible with traces greater than 50mil.

6. Keep the IN and GND pads connected with

large copper traces to achieve better thermal

performance.

7. Add

several

vias

with

10mil_drill/18mil_copper_width close to the

IN and GND pads to help with thermal

dissipation.