MP5455 – PEAK POWER ASSIST FOR LOW-POWER APPLICATIONS

MP5455 Rev. 1.01

www.MonolithicPower.com

14

2/2/2018

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PCB Layout Guidelines

(7)

Efficient PCB layout is critical for stable operation.

A 4-layer layout is recommended to achieve

better thermal performance and simplify layout.

For best results, refer to Figure 6 and follow the

guidelines below.

1) Use short, wide, and direct traces in the high-

current paths (VIN, VB, VBO, SW, STRG,

and GND).

2) Place the decoupling capacitor across VB

and GND as close as possible.

3) Place the decoupling capacitor across STRG

and GND as close to the pins as possible.

4) Keep the switching node SW short and away

from the feedback network.

5) Place the external feedback resistors next to

FB.

6) Keep the BST voltage path (BST, C5, and

SW) as short as possible.

NOTE:

7)

The corresponding schematic can be found on page 1. Note

that the STRG bulk capacitors C7A and C7B are not shown in

the schematic

Top Layer

Inner Layer 1

Inner Layer 2

Bottom Layer

Figure 6: Recommended Layout