LM9801CCVF datasheet(29/34 Pages) NSC

29 / 34 page

Applications Information (Continued)

80 A TYPICAL GREYSCALE APPLICATION

Figure 15 shows the interface between the LM9801 and a

typical greyscale evenodd output CCD the TCD1250 The

interface for most other CCDs will be similar the only differ-

ence being the values for the series resistors (if required)

The clamp capacitor value is determined as shown in Sec-

tion 42 The resistor values are usually given in the CCD’s

datasheet If the datasheet’s requirement is given as a par-

ticular risefall time the resistor can be chosen using the

graph of w1 w2 RS and TR Rise Times Through a Series

Resistance vs Load Capacitance

graph in the Typical

Performance Characteristics

section Given the required

rise time and the input capacitance of the input being driven

the resistor value can be estimated from the graph

TLH12814 – 42

FIGURE 15 Greyscale CCD Interface Example

These are the Configuration Register parameters recom-

mended for use as a starting point for most evenodd

CCDs

Mode e 1 (EvenOdd mode)

RS Pulse Width e 0 (1 MCLK)

RS Pulse Polarity e 0

RS Pulse Position e 10

Sample Reference Position e 14

Sample Signal Position e 8

1 w2RSTR Enable e 1111

TR Pulse Width e 0

TR-w1 Guardband e 0

TR Polarity e 0

Signal Polarity e 1

Dummy Pixels e 2

Optical Black Pixels e 5

( Value given in CCD datasheet)

The Mode is set to EvenOdd RS Pulse Width is set to its

minimum value and RS polarity is positive The timing

shown in

Figure 16 is determined by the RS SR and SS

registers The RS pulse position (RS) is set to 10 dividing

the pixel period so that the

signal portion is available for the

first 5 MCLKs following a w1 clock edge and the

black refer-

ence portion appears during the last 2 MCLKs (following the

1 MCLK wide reset pulse) Sample Reference (SR) is set to

14 so it samples the black reference just before the next w1

clock edge Sample Signal (SS) is set to 8 so it samples the

black reference just before the next reset pulse These val-

ues can be adjusted to account for differences in CCDs

CCD data delays settling time etc

but this is often not

necessary

TLH12814 – 43

FIGURE 16 Typical EvenOdd Timing

All 4 digital outputs (w1 w2 RS and TR) are enabled The

TR pulse width is set to the minimum 20 MCLKs as is the

guardband between w1 and TR Either of these settings can

be increased if necessary

The TR polarity is positive as is the RS polarity Some

CCDs may require one or both of these signals to be invert-

ed in which case the corresponding bit can be set to a ‘‘1’’

If there is an inverting buffer between the LM9801 and the

CCD these bits may be used to correct the output polarity

at the CCD Note that if w1 and w2 are inverted then w2

should be used as w1 at the CCD and w1 should be used

as w2 at the CCD (

Figure 17 )

TLH12814 – 44

FIGURE 17 w1 and w2 After Inversion

Since this is a CCD sensor the Signal Polarity is set to a 1

(inverted) to match the CCD’s output signal The number of

dummy pixels and optical black reference pixels are given in

the CCD’s datasheet The dummy pixel register should be

programmed with the number of dummy pixels in the CCD

1 (for example if the CCD has 16 dummy pixels then the

ister should be programmed with the number of optical

black pixels in the CCD

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