L5510

2/3

7

Other Features

modes

serial interfaces

DSP, servo, Ultra-DMA and buffer performance

8

DESCRIPTION

The Device is a highly integrated, automated sin-

gle-chip Drive Manager and Disk Drive Controller

IC designed for high-performance, headerless

ATA drive applications. Figure 2 shows the chip’s

main functional blocks.

Figure 2. Functional Block Diagram

Table 2. Revision History

Date

Revision

Description of Changes

December 2004

1

First Issue

DCTL

HIF

BCTL

EDAC

SERVO

DSP

SRAM

FLASH

BUFFER

SDRAM

READ

CHANNEL

ATA BUS

ROM

ROM

RAM

PERIPHERALS

(SYNC or

ASYNC)