MP6004—PRIMARY-SIDE REGULATED FLYBACK/BUCK 80V DCDC CONVERTER

MP6004 Rev. 1.0

www.MonolithicPower.com

20

4/14/2015

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The power dissipation in the snubber circuit is

estimated with Equation (23):

2

SN

K

LIM

S

1

PL

I

F

2

=×

×

×

(23)

Since R4 consumes the majority of the power,

R4 is estimated with Equation (24):

2

SN

SN

V

R4

P

=

(24)

C4.

The snubber capacitor C4 can be designed to

get appropriate voltage ripple on the snubber

using Equation (25):

SN

SN

S

V

V

R4 C4 F

Δ=

××

(25)

Generally, a 15 percent ripple is acceptable.

Buck Inductor Selection

The inductor is required to transfer the energy

between the input source and the output

capacitors. Unlike normal application where

inductors determine the inductor ripple, the

determines the speed of the current rising and

falling, which determines the switching period.

The

expected

maximum

frequency

can

determine the inductor value using Equation

(26):

IN

OUT

OUT

D1F

IN

D1F

PEAK

SW

(V

V

) (V

V )

1

L

(V

V ) I

F

−×

+

≈×

+×

(26)

frequency, which should be lower than 200 kHz

in general setting.

Output Diode Selection

The output rectifier diode supplies current to the

output capacitor when the internal MOSFET is

off. Use a Schottky diode to reduce loss due to

the diode forward voltage and recovery time.

In isolation application, the diode should be

rated for a reverse voltage greater than

Equation (27):

IN

S

D1

OUT

PD1

P

VN

VV

V

N

×

=+

+

(27)

snubber circuit for the output diode D1 is

recommended.

In buck mode, the diode reverse voltage

equates to the input voltage. A 20 percent ~ 40

percent margin is recommended.

In both applications, the current rating should

be higher than the maximum output current.

Dummy Load

When the system operates without a load in

flyback mode, the output voltage rises above

the normal operation voltage because of the

minimum switching frequency limitation. Use a

dummy load for good load regulation. A large

dummy load decreases efficiency, so the

dummy load is a tradeoff between efficiency

and load regulation. For applications using

Figure 10, a minimum load of around 10 mA is

recommended.

PCB Layout Guidelines

Efficient

PCB

layout

for

high-frequency

switching power supplies is critical. Poor layout

may result in reduced performance, excessive

EMI, resistive loss, and system instability. For

best results, refer to Figure 8 and Figure 9 and

follow the guidelines below:

For flyback application:

1. Keep the input loop as short as possible

between the input capacitor, transformer,

SW, and GND plane for minimal noise and

ringing.

2. Keep the output loop between the rectifier

diode, the output capacitor, and the

transformer as short as possible.

3. Keep the clamp loop circuit between D2, C4,

and the transformer as small as possible.

4. Place the VCC capacitor close to VCC for

the best decoupling. The current setting

resistor R3 should be placed as close to

ILIM and AGND as possible.

5. Keep the feedback trace far away from

noise sources (such as SW). The trace

connecting FB1 should be short.