MP2420―75V, 0.3A, SYNCHRONOUS STEP-DOWN CONVERTER WITH WATCHDOG

MP2420 Rev. 1.0

www.MonolithicPower.com

12

9/6/2015

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OPERATION

DC/DC SECTION:

The MP2420 is a 75V, 0.3A, synchronous step-

down, switching regulator with integrated high-

side and low-side, high-voltage power MOSFETs

(HS-FET and LS-FET, respectively). It provides a

highly efficient 0.3A output and features a wide

input voltage range, external soft-start control,

and precision current limit. It has a very low

operational quiescent current, making it suitable

for battery-powered applications.

Control Scheme

The ILIM comparator, FB comparator, and zero

current detector (ZCD) block control the PWM

and the inductor current drops to zero, the HS-

FET turns on, and the ILIM comparator begins

sensing the HS-FET current. When the HS-FET

current reaches its limit, the HS-FET turns off,

and the LS-FET and ZCD block turn on. The ILIM

comparator turns off to reduce the quiescent

current. The LS-FET and ZCD block turn off after

the 1V reference at this time, the HS-FET turns

than the 1V reference, the HS-FET remains off

Ipeak

Io increase

Figure 2: Control Scheme

Internal Regulator and BIAS

The 2.6V internal regulator powers most of the

than 3.0V, the output of the regulator is in full

supply overrides the input voltage and supplies

4.5V, BIAS powers the LS-FET driver.

Using BIAS to power the internal regulator

improves efficiency. It is recommended to

connect BIAS to the regulated output voltage

when it is in the 2.9V to 5.5V range. When the

output voltage is out of this range, an external

supply of >2.9V to >4.5V can be used to power

BIAS.

Enable (EN) Control

The MP2420 has a dedicated enable control

disables the chip (high logic). Its falling threshold

is a consistent 1.2V, and the rising threshold is

about 350mV higher. When floating, EN is pulled

down internally to GND to disable the chip.

When EN = 0V, the chip enters the lowest

shutdown current mode. When EN is higher than

zero but lower than its rising threshold, the chip

remains in shutdown mode with a slightly larger

shutdown current.

A Zener diode is connected internally from EN to

GND. The typical clamping voltage of the Zener

through a high ohm (Ω) resistor if the system

does not have another logic input acting as the

EN signal. The resistor must be designed to limit

the EN sink current to less than 150μA. Note that

there is an internal 3MΩ resistor from EN to GND,

so the external pull up resistor should be smaller

than

1.55V

3M

1.55V]

-

[V

(MIN)

IN

×

to ensure that EN can

Under-Voltage Lockout (UVLO)

chip from operating below its operational supply

voltage range. The UVLO rising threshold is

about 4.2V while its trailing threshold is about

3.75V.