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MP9928 датащи(PDF) 22 Page - Monolithic Power Systems |
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MP9928 датащи(HTML) 22 Page - Monolithic Power Systems |
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22 / 25 page ![]() MP9928—4V TO 60V SYNCHRONOUS STEP-DOWN CONTROLLER MP9928 Rev. 1.0 www.MonolithicPower.com 22 5/20/2016 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2016 MPS. All Rights Reserved. 3. Route the sensing traces (SENSE+, SENSE-) in paired way with smallest closed area. Avoid crossing noisy areas such as SW or high-side gate drive traces. Place the filter capacitor for the current sense signal as close to the IC pins as possible. 4. A short and wide type resistor is recommend for current sense. 5. VCC1 and VCC2 capacitors should be placed as close as possible to VCC1 pin and VCC2 pin. 6. Layout the gate drive traces as directly as possible. Layout the forward and return traces close together, either running side by side or on top of each other on adjacent layers to minimize the inductance of the gate drive path. 7. The ground return of input/output capacitor should be tied close with large GND copper area, and then connect to IC GND pin through single point. 8. For heavy load, suggest layout large copper, more layers and more vias for heat sink. Figure 8 shows the recommended components place for MP9928 in TSSOP20-EP package. Figure 9 shows the recommended components place for MP9928 in QFN20 package. For the layout, the corresponding schematic can be found on Figure 10. R2 R1 R9 R6 C7 C5 C4 C3 C2A C2B L2 C11 R14 M1 M2 C8 C1C C1A C1B R6 R15 R20 R19 R12 R11 R7 VIN GND VOUT GND D1 R13 Bottom Layer Top Layer Via Figure 8: Layout Recommendation 2 C2A C2B L1 R6 R15 R20 R19 R12 R11 R1 R2 C3 C4 C5 C6 C7 R8 R9 C1C D1 C11 R14 VOUT GND Bottom Layer Top Layer Via GND VIN R7 Figure 9: Layout Recommendation Design Example Below is a design example following the application guidelines for the following specifications: Table 3: Design Example VIN 6V to 60 V VOUT 5V IOUT 0A-7A The typical application circuit for VOUT = 5V in Figure 10 shows the detailed application schematic, and it is the basis for the typical performance waveforms. This circuit can work down to 4V after startup, but VOUT may drop when VIN is low due to maximum duty cycle limit. For more detailed device applications, please refer to the related Evaluation Board Datasheets |
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