MP9184 – 17A, 600KHZ, 20V WIDE INPUT RANGE ,SYNCHRONOUS BOOST CONVERTER IN ASMALL 3X4MM QFN PACKAGE

MP9184 Rev. 1.0

www.MonolithicPower.com

16

8/27/2015

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The MOSFET voltage rating should be equal to

or greater than the output voltage. The average

current rating must be greater than the maximum

load current. The peak-current rating must be

greater than the peak-inductor current. If a

Schottky diode is used as the output rectifier, the

same specifications should be considered.

Compensation

The output of the transconductance error

amplifier (COMP) is used to compensate the

regulation control system. The system uses two

poles and one zero to stabilize the control loop.

the

compensation

resistor

These

are

determined by the equations:

P1

LOAD

OUT

1

F(Hz)

2R

C







Z1

COMP

COMP

1

F(Hz)

2R

C







The DC loop gain is calculated as follows:

VEA

IN

LOAD

FB

CS

COMP

VDC

2

OUT

AV

R

V

G

R

A

(V / V)

2V













regulation threshold.

exists in continuous conduction mode (CCM).

The inductor current does not drop to zero each

cycle. The frequency of the right-half plane zero

is:

2

LOAD

IN

RHP

OUT

R

V

F(

) (Hz)

2L

V





The right-half-plane zero increases the gain and

reduces the phase simultaneously, resulting in a

smaller phase and gain margin. The worst case

happens during conditions of minimum input

voltage and maximum output power.

Compensation recommendations are listed in the

“Typical Application Circuits” section.

PCB Layout Guide

High-frequency switching regulators require very

careful PCB layout for stable operation and low

noise. All components must be placed as close to

the IC as possible.

Route on bottom layer

SW

SW

PGND

PGND

PGND

SW

PGND

PGND

SW

SW

1

2

3

4

5

6

7

8

1

2

2

1

1

2

1

2

2

1

2

1

1

2

C1

1

2

R4

GND

L1

U1

Q1

C2

R2

C4

C6

Figure 4. PCB Layout Reference

Refer to Figure 4 and the guidelines below to

optimize performance:

1. Keep the output loop (SW, PGND, Q1, and

C2) as small as possible.

2. Place FB divider R1 and R2 as close as

possible to FB.

3. Route the sensing traces (SENSE and IN) in

parallel closely with a small closed area. The

0805 package is recommended

for the

sensing resistor (R4) to reduce parasitic

inductance.

4. Connect FB and OUT feedback from the

output capacitor (C2).

5. Connect the compensation components and

SS capacitor to AGND with a short loop.

6. Connect the VDD capacitor to AGND with a

short loop. Do not connect to PGND net

before connecting to IC-AGND.

7. Connect the compensation components and

SS capacitor to AGND with a short loop.