VIA Technologies, Inc.

Preliminary VT83C469

13

Card Status Change Register ( Read Only )

Address : Index ( Base + 04h )

D[7:4]

R. 0000

D3

Card Detect Change.

0: No change detected on either CD2# or CD1#.

1: A change has been detected on CD2# and CD1#.

D2

Ready Change.

0: No change on RDY/BSY#, or I/O PC Card installed.

1: When a low to high has been detected on the RDY/BSY# signal indicating that the memory PC

Card is ready to accept a new data transfer.

D1

Battery Warning.

0: No battery warning condition, or I/O PC Card installed.

1: A battery warning condition has been detected.

D0

Battery Dead ( STSCHG# )

For memory PC Cards, bit is set one when a battery dead condition has been detected.

For I/O PC Cards, bit is set to one if ring indicate enable bit in the interrupt and general control

register is set to zero and the STSCHG/RI# signal from the I/O PC Card has been pulled low. The

system software then has to read the status change register in the PC Card to determine the cause of

the status change signal STSCHG#. This bit reads zero for I/O PC Cards if the ring indicate enable

bit in the interrupt and general control register is set to one.

NOTE :

The Card Status Change Register contains the status for sources of the card status change

interrupt. These sources can be enabled to generate a card status change interrupt by setting the

corresponding bit in the card status change interrupt configuration register. Reading the Card

Status Change Register causes the register bits to be reset to zero.

If the card status change interrupt is enabled to one of the system bus interrupt request lines,

the corresponding IRQ signal remains active high until this register is read.