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MP8845CGC датащи(PDF) 5 Page - Monolithic Power Systems

номер детали MP8845CGC
подробное описание детали  5A High Efficient Synchronous Step-Down Switchers with I2C Interface
PDF  20 Pages
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производитель  MPS [Monolithic Power Systems]
домашняя страница  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP8845CGC датащи(HTML) 5 Page - Monolithic Power Systems

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MP8845C – 5A HIGH EFFICIENT SYNC. STEP DOWN SWITCHER WITH I2C
MP8845C Rev. 1.02
www.MonolithicPower.com
5
4/25/2014
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2014 MPS. All Rights Reserved.
I/O LEVEL CHARACTERISTICS
(continued)
Parameter
Symbol
Condition
HS-Mode
LS-Mode
Units
Min
Max
Min
Max
Fall time of SDAH signal
tfDA
Capacitive load from
10pF to 100pF
10
80
-
-
ns
Capacitive load of
400pF
20
160
20
250
ns
Pulse width of spikes that
must be suppressed by
the input filter
tSP
0
10
0
50
ns
Input current each I/O pin
Ii
Input voltage between
0.1Vcc and 0.9Vcc
-
10
-10
+10
uA
Capacitance for each I/O
pin
Ci
-
10
-
10
pF
I2C PORT SIGNAL CHARACTERISTICS
Parameter
Symbol
Condition
Cb=100pF
Cb=400pF
Units
Min
Max
Min
Max
SCLH and SCL clock
frequency
fSCHL
0
3.4
0
0.4
MHz
Set-up time for a
repeated START
condition
TSU;STA
160
-
600
-
ns
Hold time (repeated)
START condition
THD;STA
160
-
600
-
ns
Low period of the SCL
clock
tLOW
160
-
1300
-
ns
High period of the SCL
clock
tHIGH
60
-
600
-
ns
Data set-up time
TSU:DAT
10
-
100
-
ns
Data hold time
THD;DAT
0
70
0
-
ns
Rise time of SCLH signal
trCL
10
40
20*0.1Cb
300
ns
Rise time of SCLH signal
after a repeated START
condition and after an
acknowledge bit
tfCL1
10
80
20*0.1Cb
300
ns
Fall time of SCLH signal
TfCL
10
40
20*0.1Cb
300
ns
Rise time of SDAH signal
tfDA
10
80
20*0.1Cb
300
ns



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