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MP4575GF датащи(PDF) 16 Page - Monolithic Power Systems

номер детали MP4575GF
подробное описание детали  5A, 4.5V - 55V Input, Frequency-Programmable, Fully Integrated, Synchronous, Step-Down Converter
PDF  22 Pages
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производитель  MPS [Monolithic Power Systems]
домашняя страница  http://www.monolithicpower.com
Logo MPS - Monolithic Power Systems

MP4575GF датащи(HTML) 16 Page - Monolithic Power Systems

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MP4575
– 5A, 55V, SYNCHRONOUS, STEP-DOWN CONVERTER
MP4575 Rev. 1.0
www.MonolithicPower.com
16
8/16/2016
MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2016 MPS. All Rights Reserved.
threshold (valley current limit). This is useful for
preventing an inductor current runaway. Both
the peak current limit and the valley current limit
values are dependent on the FB voltage. If the
feedback
output
voltage
is
higher
than
50%xREF, the current limit value is normal. If
the feedback output voltage is lower than
50%xREF, the current limit decreases to half
the normal value when the feedback output
voltage is zero. This feature is useful for
reducing OCP thermal dissipation, which may
worsen when the output voltage is shorted. It is
also useful for reducing high inrush current
during start-up.
Under-Voltage Lockout (UVLO) Protection
The
MP4575
has
an
input
under-voltage
lockout (UVLO) protection. When EN is active,
the MP4575 is powered on when the input
voltage is higher than the UVLO rising threshold,
and is powered off when the input voltage drops
below the UVLO falling threshold.
Thermal Shutdown Protection
The thermal shutdown is employed in the
MP4575 by monitoring the IC temperature
internally. If the junction temperature exceeds
the threshold (typically 170°C), the regulator
shuts
off
and turns on
again
when
the
temperature drops below 160°C. There is a
hysteresis of about 10°C.
Power Good (PG)
The MP4575 uses one power good (PG) pin out
to indicate normal operation after the soft-start
time.
PG is the open drain of the internal MOSFET.
PG should be connected to VDD or an external
voltage source through a resistor (i.e.: 100k
Ω).
After the input voltage is applied, the MOSFET
is turned on, and PG is pulled to GND before
SS is ready. After the FB voltage reaches 90%
of the REF voltage, the MOSFET turns off, and
PG is pulled high by an external voltage source.
When the FB voltage drops to 85% of the REF
voltage, the PG voltage is pulled to GND to
indicate a failure output status.
Floating Driver and Bootstrap Charging
An external bootstrap capacitor (typically 0.1µF)
between BST and SW powers the floating
power MOSFET driver. This floating driver has
its own UVLO protection. This UVLO’s rising
threshold is 2.3V with a hysteresis of 300mV.
The driv
er’s UVLO is soft-start related. When
the
bootstrap
voltage
reaches
its
UVLO
threshold, the soft-start circuit resets. When the
bootstrap UVLO is removed, the soft-start reset
is off, and the soft-start process resumes.
The
dedicated
internal
bootstrap
regulator
regulates and charges the bootstrap capacitor
to 4.2V. When the voltage between the BST
and SW nodes is less than its regulation, a
PMOS pass transistor from VIN to BST turns
on. The charging current path is from VIN to
BST to SW.
As long as VIN is sufficiently higher than VSW,
the bootstrap capacitor can be charged. When
the HS-FET is on, VIN
≈ VSW, so the bootstrap
capacitor cannot be charged. When the LS-FET
is on, the difference between VIN and VSW is at
its largest, making this the best period to
charge. When there is no current in the
inductor, VSW = VOUT, so the difference between
VIN
and
VOUT
can
charge
the
bootstrap
capacitor.
At higher duty cycles, the time period available
for bootstrap charging is shorter,
so the
bootstrap capacitor may not be sufficiently
charged. If the internal circuit does not have
sufficient voltage, and the bootstrap capacitor is
not charged, extra external circuitry can be
used to ensure that the bootstrap voltage is
within the normal operating region.



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