MP4430

– 36V, 3.5A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER

MP4430 Rev. 1.01

www.MonolithicPower.com

19

1/12/2018

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Error Amplifier (EA)

outputs a current proportional to the difference

between the two. This output current then

charges

or

discharges

the

internal

controls the power MOSFET current. The

optimized

internal

compensation

network

minimizes the external component count and

simplifies the control loop design.

Internal Regulator and BIAS

Most of the internal circuitry is powered on by

the 5V internal regulator. This regulator takes

the VIN input and operates in the full VIN range.

When VIN exceeds 5V, the output of the

regulator is in full regulation. When VIN falls

below 5V, the output decreases following VIN.

A decoupling ceramic capacitor is needed close

to VCC.

For better thermal performance, connect BIAS

to an external power supply between 5V and

18V. The BIAS supply overrides VIN to power

the internal regulator. Using the BIAS supply

allows VCC to be derived from a high-efficiency

connect BIAS to ground if not used.

Under-Voltage Lockout (UVLO)

Under-voltage lockout (UVLO) protects the chip

from operating at an insufficient supply voltage.

The UVLO comparator monitors the output

voltage of the internal regulator (VCC). The

UVLO rising threshold is about 2.8V with a

150mV hysteresis.

Enable Control (EN)

EN is a digital control pin that turns the

regulator on and off. When EN is pulled below

its threshold voltage, the chip is put into the

lowest shutdown current mode. Pulling EN

above its threshold voltage turns on the part.

Do not float EN.

Power Good Indicator (PG)

The MP4430 has a power good (PG) indicator.

PG is the open drain of a MOSFET and should

be connected to VCC or another voltage source

through

a

resistor

(e.g.:

100kΩ). In the

presence of an input voltage, the MOSFET

turns on so that PG is pulled low before SS is

ready. When the regulator output is within

±10% of its nominal output, the PG output is

pulled high after a delay, typically 30

μs. When

the output voltage moves outside of this range

with a hysteresis, the PG output is pulled low

with a 50

μs delay to indicate a failure output

status.

Programmable Frequency

The oscillating frequency of the MP4430 can be

programmed either by an external frequency

clock. The frequency resistor should be located

between FREQ and ground as close as to the

device as possible.

Equation (1):

FREQ

1.11

SW

170000

R

(k

Ω)

f

(kHz)



(1)

The calculated resistance may need fine-tuning

during the bench test.

FREQ is not allowed to be floated even if an

external SYNC clock is added.

SYNC and PHASE

The

internal

oscillator

frequency

can

be

synchronized to an external clock ranging from

350kHz up to 2.5MHz through SYNC. The

external clock should be at least 250kHz larger

high amplitude of the SYNC clock is higher than

1.8V, and the low amplitude is lower than 0.4V.

There is no pulse width requirement, but there

is always parasitic capacitance of the pad, so if

the pulse width is too short, a clear rising and

falling edge may not be seen due to the

parasitic capacitance. A pulse longer than

100ns is recommended in application.

PHASE is used when two or more MP4430

devices are in parallel with the same SYNC

clock. Pulling PHASE high forces the device to

operate in-phase of the SYNC clock. Pulling it

low forces the device to be 180°out-of-phase of

the SYNC clock. By setting different voltages

for PHASE, two devices can operate 180°out-

of-phase to reduce the total input current ripple

so a smaller input bypass capacitor can be

used

(see

Figure

4).

The

PHASE

rising

threshold

is

about

2.5V

with

a

400mV

hysteresis.