MP2263

– 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER

MP2263 Rev. 1.0

www.MonolithicPower.com

15

6/22/2016

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Selecting the Output Capacitor

The output capacitor (C2) maintains the DC

output voltage. Use ceramic, tantalum, or low

ESR electrolytic capacitors. For best results,

use low ESR capacitors to keep the output

voltage ripple low. The output voltage ripple can

be estimated with Equation (9):

OUT

OUT

OUT

ESR

S

1

IN

S

VV

1

V

1

R

f

L

V

8 f

C2









 











 

 

(9)

equivalent series resistance (ESR) value of the

output capacitor.

For

ceramic

capacitors,

the

capacitance

dominates the impedance at the switching

frequency, and the capacitance causes the

majority of the output voltage ripple. For

simplification, the output voltage ripple can be

estimated with Equation (10):

OUT

OUT

OUT

2

IN

S1

VV

ΔV

1

V

8 f

L

C2





 





 



(10)

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be approximated with Equation (11):

OUT

OUT

OUT

ESR

IN

S1

VV

ΔV

1

R

f

L

V





 









(11)

The characteristics of the output capacitor

affect the stability of the regulation system. The

MP2263 can be optimized for a wide range of

capacitance and ESR values.

PCB Layout Guidelines

(8)

Efficient

PCB

layout

is

critical for

stable

operation. For best results, refer to Figure 6 and

follow the guidelines below.

1) Keep the connection of the input ground

and GND as short and wide as possible.

2) Keep the connection of the input capacitor

and IN as short and wide as possible.

3) Ensure all feedback connections are short

and direct.

4) Place

the

feedback

resistors

and

compensation components as close to the

chip as possible.

5) Route SW away from sensitive analog

areas, such as FB.

NOTE:

8)

The recommended layout is based on Figure 8.

To achieve better performance, use four-layer

boards. Figure 6 shows the top and bottom

layers (Inner 1 and Inner 2 are both GND).

GND

GND

VOUT

VIN

Top Layer

GND

Bottom Layer

Figure 6: Sample PCB Layout

Design Example

Table 2 shows a design example following the

application guidelines for the specifications

below:

Table 2: Design Example

12V

3.3V

Io

3A

The detailed application schematic is shown in

Figure 8. The typical performance and circuit

waveforms

are

shown

in

the

Typical

Performance

Characteristics

section.

For

additional device applications, please refer to

the related evaluation board datasheets.