MP2263

– 30V, 3A, LOW IQ, SYNCHRONOUS, STEP-DOWN CONVERTER

MP2263 Rev. 1.0

www.MonolithicPower.com

12

6/22/2016

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2016 MPS. All Rights Reserved.

LDO1

LDO2

VIN

BIAS

VCC

EN1

EN2

D1

Figure 3: VCC Regulator

Bootstrap Charging

The bootstrap capacitor is charged and regulated

to about 5V by the dedicated internal bootstrap

regulator. When the voltage between the BST

and SW nodes is lower than its regulation, a

PMOS connected from VCC to BST is turned on.

The charging current path is from VCC to BST to

SW.

When the HS-FET is on, VIN is about equal to

SW, so the bootstrap capacitor cannot be

charged.

At higher duty cycle operation conditions, the

time period available to the bootstrap charging is

less, so the bootstrap capacitor may not be

charged sufficiently. In case the internal circuit

does not have sufficient voltage or time to charge

the bootstrap capacitor, extra external circuitry

can be used to ensure that the bootstrap voltage

is in the normal operation region.

Low-Dropout Operation

To improve dropout, the MP2263 is designed to

operate at almost 100% duty cycle for as long as

the BST to SW voltage is greater than 2.5V.

When the voltage from BST to SW drops below

2.5V, the HS-FET is turned off using an UVLO

circuit, which allows the LS-FET to conduct and

refresh the charge on the BST capacitor. In DCM

or PSM, the LS-FET is forced on to refresh the

BST voltage.

Since the supply current sourced from the BST

capacitor is low, the HS-FET can remain on for

more switching cycles than are required to

refresh the capacitor. Therefore, the effective

duty cycle of the switching regulator is high.

The effective duty cycle during dropout of the

regulator is mainly influenced by the voltage

drops across the power MOSFET, inductor

resistance, low-side diode and printed circuit

board resistance.

Enable Control (EN)

EN is a digital control pin that turns the regulator

on and off.

EN can be enabled by an external logic H/L

signal. When EN is pulled below the threshold

voltage, the chip enters the lowest shutdown

current

mode.

Forcing

EN

above

the

EN

threshold voltage turns on the MP2263.

For the programmable VIN under-voltage lockout

(UVLO), with a high enough VIN, the MP2263

can be enabled and disabled by EN (see Figure

4). This circuit can generate a programmable VIN

UVLO and hysteresis.

EN

Figure 4: Enable Divider Circuit

Frequency Programmable

The

MP2263

oscillating

frequency

is

the FREQ pin to ground.

with Equation (1):

freq

s

86500

R

(k )

6.5

f (kHz)

 



(1)

Soft Start (SS)

Soft start (SS) is implemented to prevent the

converter

output

voltage

from

overshooting

during start-up.

When the soft-start period begins, an internal

current source begins charging the external soft-

start

capacitor.

After

the

soft-start

voltage

charges higher than the internal offset voltage