Rev 1.2

Page 2 of 10

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Table 1. Electrical Characteristics (continuous)

Parameters

Symbol

Min.

Typ.

Max.

Unit

Condition

LVCMOS Output Characteristics

Duty Cycle

DC

45

–

55

%

Rise/Fall Time

[3]

T_r, T_f

–

4

8

ns

Vdd = 1.8V, 20% - 80%. Contact SiTime for other

programmable rise/fall options

–

–

8

ns

Vdd = 2.25V to 3.63V, 20% - 80%. Contact SiTime for other

programmable rise/fall options

Output High Voltage

VOH

90%

–

–

VDD

IOH = -0.5 mA (Vdd = 1.8V)

IOH = -1.2 mA (Vdd = 2.25V to 3.63V)

Output Low Voltage

VOL

–

–

10%

VDD

IOL = 0.5 mA (Vdd = 1.8V)

IOL = 1.2 mA (Vdd = 2.25V to 3.63V)

Input Characteristics

Input High Voltage

VIH

80%

–

–

VDD

Input Low Voltage

VIL

–

–

20%

VDD

Input Slew Rate

In-slew

10

–

–

V/µs

Input Pull-down Impedance

Z_in

300

–

–

kΩ

Active mode (ST pin = LOW), Vdd = 1.8V

270

–

–

kΩ

Active mode (ST pin = LOW), Vdd = 2.25V to 3.63V

2.5

–

–

MΩ

Standby mode (ST pin = HIGH), Vdd = 1.8V

1.3

–

–

MΩ

Standby mode (ST pin = HIGH), Vdd = 2.25V to 3.63V

Startup, Standby and Resume Timing

Startup Time

T_start

–

75

150

ms

Measured from the time VDD reaches 90% of its final value

Standby Time

T_stdby

–

–

20

µs

Measured from the time ST pin crosses 50% threshold

Resume Time

T_resume

–

2

3

ms

Measured from the time ST pin crosses 50% threshold

Jitter

RMS Period Jitter

[3]

T_jitt

–

75

110

ps

f = 6.144 MHz, Vdd = 1.8V

–

–

110

ps

f = 6.144 MHz, Vdd = 2.25V to 3.63V

RMS Phase Jitter

[3]

T_phj

–

0.8

2.5

ns

f = 6.144 MHz, Vdd = 1.8V,

Integration bandwidth = 100 Hz to 40 kHz

[2]

–

–

2.5

ns

f = 6.144 MHz, Vdd = 2.25V to 3.63V,

Integration bandwidth = 100 Hz to 40 kHz

[2]

Notes:

1.

Current consumption with load is a function of the output frequency and output load. For any given output frequency, the capacitive loading will increase

current consumption equal to C_load*VDD*f(MHz).

2.

Max spec inclusive of 25 mV peak-to-peak sinusoidal noise on VDD. Noise frequency 100 Hz to 20 MHz.

3.

Refer to the performance plot section for typical values at 2.5, 2.8, 3.0 and 3.3V condition

Table 2. Pin Description

Pin

Symbol

Functionality

1

ST

Input

L: Specified frequency output

H: Output is low (weak pull down). Device goes to the standby mode.

Supply current reduces to I_std.

2

OUT

Output

LVCMOS clock output

3

VDD

Power

Supply voltage. Bypass with a 0.01µF X7R capacitor.

4

GND

Power

Connect to ground

Top View

GND

VDD

OUT

ST

1

4

2

3

Figure 1. Pin Assignments