MP21148 – 1A, SYNCHRONOUS, STEP-DOWN CONVERTER WITH CCM

MP21148 Rev. 1.1

www.MonolithicPower.com

12

2/16/2017

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

© 2017 MPS. All Rights Reserved.

For simplification, choose an input capacitor

with an RMS current rating greater than half of

the maximum load current.

The input capacitor can be electrolytic, tantalum,

or ceramic. When using electrolytic or tantalum

capacitors, add a small, high-quality

0.1μF

ceramic capacitor as close to the IC as possible.

When using ceramic capacitors, ensure that

they have enough capacitance to provide a

sufficient charge to prevent excessive voltage

ripple at the input. The input voltage ripple

caused by capacitance can be estimated with

Equation (7):

LOAD

OUT

OUT

IN

IN

S

IN

I

V

V

V1

f

C1

V

V









 







(7)

Selecting the Output Capacitor

The output capacitor (C2) stabilizes the DC

output

voltage.

Ceramic

capacitors

are

recommended. For best results, use low ESR

capacitors to limit the output voltage ripple. The

output voltage ripple can be estimated with

Equation (8):

OUT

OUT

OUT

ESR

S

1

IN

S

VV

1

V

1

R

f

L

V

8 f

C2









 











 

 

(8)

equivalent series resistance (ESR) value of the

output capacitor.

When

using

ceramic

capacitors,

the

capacitance dominates the impedance at the

switching frequency and causes most of the

output voltage ripple. For simplification, the

output voltage ripple can be estimated with

Equation (9):

OUT

OUT

OUT

2

S

1

IN

VV

ΔV1

8 f

L

C2

V





 





 



(9)

For tantalum or electrolytic capacitors, the ESR

dominates the impedance at the switching

frequency. For simplification, the output ripple

can be approximated with Equation (10):

OUT

OUT

OUT

ESR

IN

S1

VV

ΔV

1

R

f

L

V





 









(10)

The characteristics of the output capacitor also

affect the stability of the regulation system.

PCB Layout Guidelines

Efficient

PCB

layout

is

critical for

stable

operation. For the high-frequency switching

converter, a poor layout design can result in

poor line or load regulation and stability issues.

For best results, refer to Figure 3 and follow the

guidelines below.

1. Place the high-current paths (GND, IN, and

SW) very close to the device with short,

direct, and wide traces.

2. Place the input capacitor as close to IN and

GND as possible.

3. Place the external feedback resistors next

to FB.

4. Keep the switching node SW short and

away from the feedback network.

possible or keep it away from the power

inductor.

Lout

2

1

3

5

6

4

VIN

SW

GND

EN

OUT

FB

Cout

R1

GND

R2

Vin

Vout

EN

Cin

Figure 3: Two Ends of Input Decoupling

Capacitor Close to Pin 2 and Pin 3