ATAR092 datasheet(49/100 Pages) ATMEL

49 / 100 page

ATAR092/ATAR892

4535C–4BMCU–02/04

Timer 3 – Mode 8:

FSK Modulation with Shift Register Data (SO)

The two compare registers are used for generating two different time intervals. The SSI

internal data output (SO) selects which compare register is used for the output fre-

quency generation. A ‘0’ level at the SSI data output enables the compare register 1. A

‘1’ level enables compare register 2. The compare- and compare mode registers must

be programmed to generate the two frequencies via the output toggle flip-flop. The SSi

can be supplied with the toggle signal of Timer 2. The Timer 3 counter is driven by an

internal or external clock source. The Timer 2 counter is driven by the Counter 3 (TOG3)

(see also combination mode 13).

Figure 51. FSK Modulation

Timer 3 – Mode 9:

Pulse-width Modulation with the Shift Register

The two compare registers are used for generating two different time intervals. The SSI

internal data output (SO) selects which compare register is used for the output pulse

generation. In this mode both compare- and compare mode registers must be pro-

grammed for generating the two pulse widths. It is also useful to enable the single-action

mode for extreme duty cycles. Timer 2 is used as baudrate generator and for the trigger

restart of Timer 3. The SSI must be supplied with a toggle signal of Timer 2. The counter

is driven by an internal or external clock source (see combination mode 7).

Figure 52. Pulse-width Modulation

012340 1 23401 2 3

Counter 3

CM31

CM32

40 1 2 0 1 2012 0 120 1 201201 20 1 2 3

T3R

T3O

000 00 00 0 0

00 0 0

Counter 3

CM31

CM32

T3O

00 0 001 234 5 6 7 8 9101112131415 0 12 345

TOG2

67 8

1112

2 3

SIR

SCO

T3R

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