P89LPC904FD datasheet(26/41 Pages) PHILIPS

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Philips Semiconductors

P89LPC904

8-bit microcontrollers with two-clock accelerated 80C51 core

Preliminary data

Rev. 02 — 25 June 2004

26 of 41

9397 750 13521

reaches all logic 0s, the counter will be reloaded again and the RTCF ﬂag will be set.

The clock source for this counter is the CPU clock (CCLK). Only power-on reset will

reset the Real-Time clock and its associated SFRs to the default state.

8.19 UART

The P89LPC904 has an enhanced UART that is compatible with the conventional

80C51 UART except that Timer 2 overﬂow cannot be used as a baud rate source.

The P89LPC904 does include an independent Baud Rate Generator. The baud rate

can be selected from the oscillator (divided by a constant), Timer 1 overﬂow, or the

independent Baud Rate Generator. In addition to the baud rate generation,

enhancements over the standard 80C51 UART include Framing Error detection,

automatic address recognition, selectable double buffering and several interrupt

options. The UART can be operated in 4 modes: shift register, 8-bit UART, 9-bit

UART, and CPU clock/32 or CPU clock/16.

8.19.1

Mode 0

Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are

transmitted or received, LSB ﬁrst. The baud rate is ﬁxed at 1

⁄

16 of the CPU clock

frequency.

8.19.2

Mode 1

10 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0),

8 data bits (LSB ﬁrst), and a stop bit (logic 1). When data is received, the stop bit is

stored in RB8 in Special Function Register SCON. The baud rate is variable and is

determined by the Timer 1 overﬂow rate or the Baud Rate Generator (described in

Section 8.19.5 “Baud rate generator and selection”).

8.19.3

Mode 2

11 bits are transmitted (through TxD) or received (through RxD): start bit (logic 0),

8 data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). When

data is transmitted, the 9th data bit (TB8 in SCON) can be assigned the value of

logic 0 or logic 1. Or, for example, the parity bit (P, in the PSW) could be moved into

TB8. When data is received, the 9th data bit goes into RB8 in Special Function

either 1

⁄

16 or

⁄

32 of the CPU clock frequency, as determined by the SMOD1 bit in

PCON.

8.19.4

Mode 3

11 bits are transmitted (through TxD) or received (through RxD): a start bit (logic 0), 8

data bits (LSB ﬁrst), a programmable 9th data bit, and a stop bit (logic 1). In fact,

Mode 3 is the same as Mode 2 in all respects except baud rate. The baud rate in

Mode 3 is variable and is determined by the Timer 1 overﬂow rate or the Baud Rate

Generator (described in Section 8.19.5 “Baud rate generator and selection”).

8.19.5

Baud rate generator and selection

The P89LPC904 enhanced UART has an independent Baud Rate Generator. The

baud rate is determined by a baud-rate preprogrammed into the BRGR1 and BRGR0

SFRs which together form a 16-bit baud rate divisor value that works in a similar

manner as Timer 1. If the baud rate generator is used, Timer 1 can be used for other

timing functions.

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