October 20, 1997

Version 1.6

7

OV5017

Confidential Preliminary Product Specification

TO1

STA6

Reserved bit.

OV

STA3

Pixel data overrun flag. It is set each time pixel data is updated if

STA0 has been set already. Reading of this register clears the bit.

VSYNC

STA2

This bit duplicates the signal at pin VSYNC.

HREF

STA1

This bit duplicates the signal at pin HREF.

RDY

STA0

This bit is set each time pixel data is updated, and is cleared by read-

ing the VPORT register. This bit will not be set if the VPORT register

is being read while pixel data is updating.

FCTL

FSET

FCTL[7]

Set to initiate single frame transfer. This bit works only if FCTL[6] is

also set. If this bit is set in the middle of a frame,

asserted until the next new frame. This bit is cleared automatically at

the end of the new frame so that it can be set again.

SFR

FCTL[6]

Set to enable single frame operation mode. Since the video data is a

continuous non-stop byte stream, the validity of the data is qualified

only by assertion of

is asserted in every frame. In a single frame operation,

asserted only for the first frame immediately after setting the FCTL[7].

The actual duration of

size.

SKIP

FCTL[3]

Makes

does not alter the pixel rate; it simply blocks their assertion in every

other frame.

FBLC

FCTL[2]

Chooses how frequent the black level calibration is performed inter-

nally. It is set once every frame and cleared once every line. Line BLC

can set the BLC within a fraction of a frame time. This is useful to

speed up BLC process after power up or activation after standby

mode. However, frame BLC provides better image stability.

STOP

FCTL[1]

Set to stop chip clock and enter low power standby mode. This func-

tion does not alter register content. The chip is put in default state and

all image data is lost. Setting this bit does not prevent further register

access. Upon clearing this bit, it generally takes about two frames for

the chip to become stable.

SRST

FCTL[0]

Software reset enable. Setting this bit resets all the on-chip registers

and puts the chip in default state. Upon clearing this bit, it generally

takes about two frames for the chip to become stable.

Table 3. Bit descriptions (Continued)

Register

Name

Bit name

Range

Function