TLF5301

January 1988

MM54HC42MM74HC42

BCD-to-Decimal Decoder

General Description

This decoder utilizes advanced silicon-gate CMOS technol-

ogy Data on the four input pins select one of the 10 outputs

corresponding to the value of the BCD number on the in-

puts An output will go low when selected otherwise it re-

mains high If the input data is not a valid BCD number all

outputs will remain high The circuit has high noise immunity

and low power consumption usually associated with CMOS

circuitry yet also has speeds comparable to low power

Schottky TTL (LS-TTL) circuits and is capable of driving 10

LS-TTL equivalent loads

All inputs are protected from damage due to static dis-

Features

Y

Typical propagation delay 15 ns

Y

Wide supply range 2V – 6V

Y

Low quiescent current 80 mA (74HC)

Y

Fanout of 10 LS-TTL loads

Connection Diagram

Dual-in-line Package

TLF5301 – 1

Top View

Order Number MM54HC42 or MM74HC42

Truth Table

No

Inputs

Outputs

D C B A

0

1

23456789

LLLLL H H HHHHHHH

L

L

L HH L H HHHHHHH

L

LHLH HL HHHHHHH

L

L HHHHH L HHHHHH

L H L

L HHHH L HHHHH

L H L HHHHHH L HHHH

L HH L HHHHHH L HHH

L HHHHHHHHHH L H H

H L

L

L HHHHHHHH L H

H L

L HHHHHHHHHH L

HLHLH H H HHHHHHH

H L HHHHHHHHHHHH

INVALID

HH L

L HHHHHHHHHH

HH L HHHHHHHHHHH

HHH L HHHHHHHHHH

HHHHHHHHHHHHHH

Logic Diagram

TLF5301 – 2

C1995 National Semiconductor Corporation

RRD-B30M105Printed in U S A