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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LM12434CIWM датащи(PDF) 63 Page - National Semiconductor (TI) |
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LM12434CIWM датащи(HTML) 63 Page - National Semiconductor (TI) |
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63 / 80 page  70 Digital Interface (Continued) Burst read cycle A burst read cycle starts the same way as a single read cycle but the B bit in the command packet is set to one indicating a burst read cycle After the first 16 bits of data carrying the command packet is written to the DAS the DAS begins to send out the data words from the addressed register on the DR line repeatedly Each data word is preceded by an FSR pulse for synchronization To terminate a burst read cycle the processor does a dummy read from the configuration register during the last data word This dummy read should be started so that its FSR pulse occurs during the 15th to 17th SCLK cycle of the last data word as shown in Figure 15c The dummy read terminates the burst read cycle and shifts out the contents of the configuration register on the DR line This data can be discarded After transfer of the last data bit from the config- uration register the DAS is ready for a new communication cycle to begin TLH11879 – 47 (a) Write Cycle TLH11879 – 48 (b) Read Cycle FIGURE 15 Timing Diagram for LM12434 and LM12 L 438 TMS320 Serial Interface Mode 63 |
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