SIP41103DM datasheet(6/8 Pages) VISHAY

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Document Number: 72718

S-

61692–Rev. E, 04-Sep-06

Vishay Siliconix

SiP41103

on LX falls below 1 V by the inductor action, the low-

side driver is enabled and OUTL goes high after some

delay. When the signal on PWM goes high, OUTL will

go low after an internal propagation delay. After the

voltage on OUTL drops below 1 V the high-side driver

is enabled OUTH will go high after an internal propaga-

tion delay. If LX does not drop below 1 V within 400 ns

after OUTH goes low, OUTL is forced high until the next

PWM transition.

Delay

The addition of a capacitor between DELAY and GND

will increase the propagation delay time for OUTH

going high. Delay capacitance may be added to pre-

vent shoot-through current in the low-side MOSFET

due to the finite time between OUTL going low and the

continuing conduction of the low-side MOSFET.

Choose a MOSFET with lower gate resistance to

reduce this effect. If necessary, choose a capacitor

value that prevents MOSFET conduction under worst-

case temperature and manufacturing conditions. Prop-

agation delay is increased according to the ratio of

1.2 ns/pF.

Synchronous MOSFET Enable

Under

light

load

conditions,

efficiency

can

increased by disabling the synchronous MOSFET,

thus avoiding the gate charge losses of the synchro-

nous MOSFET. When ENSYNC is low, OUTL is forced

low. When high, the low-side driver operates normally.

ENSYNC should be driven by a 5-V signal.

Shutdown

The driver enters shutdown mode when a period of

inactivity on PWM elapses. Shutdown current is less

than 1 µA.

VDD Bypass Capacitor

MOSFET drivers draw large peak currents from the

supplies when they switch. A local bypass capacitor is

required to supply this current and reduce power sup-

ply noise. Connect a 1 µF ceramic capacitor as close

as practical between the VDD and GND pins.

Undervoltage Lockout

Undervoltage lockout prevents control of the circuit

until the supply voltages reach valid operating levels.

The UVLO circuit forces OUTL and OUTH to low when

VDD is below its specified voltage. A separate UVLO

forces OUTH low when the voltage between BOOT

and LX is below the specified voltage.

Thermal Protection

If the temperature rises above 165 °C, the thermal pro-

tection disables the drivers. The drivers are re-enabled

after the temperature has decreased below 140 °C.

TYPICAL CHARACTERISTICS

IDD vs. CLOAD vs. Frequency

1234

CLOAD (nF)

1 MHz

500 kHz

200 kHz

High Side Turn On Delay vs. CDELAY

0.0

20.0

40.0

60.0

80.0

100.0

120.0

140.0

1020304050

60708090 100 110

CDelay (pF)

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