AD9876BSTRL datasheet(21/24 Pages) AD

21 / 24 page

REV. A

AD9876

–21–

Bit 5: Software Reset

Setting this bit high resets the chip. The PLLs will relock to the

input clock and all registers (except Register 0

× 0, Bit 6) revert to

their default values. Upon completion of the reset, Bit 5 is reset to 0.

The content of the interpolator stages are not cleared by software

or hardware resets. It is recommended to “flush” the transmit

path with zeros before transmitting data.

Bit 6: SPI LSB First

Setting this bit high causes the serial port to send and receive

data least significant bit (LSB) first. The default low state con-

figures the serial port to send and receive data most significant

bit (MSB) first.

REGISTERS 1 AND 2—POWER-DOWN

The combination of the PWR DN pin and Registers 1 and 2

allow for the configuration of two separate pin selectable power

settings. The PWR DN pin selects between two sets of individually

programmed operation modes.

When the PWR DN pin is low, the functional blocks corre-

sponding to the bits set in Register 1 will be powered down.

When the PWR DN pin is high, the functional blocks corre-

sponding to the bits set in Register 2 will be powered down.

Bit 0: Power-Down Receive Filter and CPGA

Setting this bit high powers down and bypasses the Rx LPF and

coarse programmable gain amplifier.

Bit 1: Power-Down ADC and FPGA

Setting this bit high powers down the ADC and fine program-

mable gain amplifier (FPGA).

Bit 2: Power-Down Rx Reference

Setting this bit high powers down the ADC reference. This bit

should be set if an external reference is applied.

Bit 3: Power-Down Interpolators

Setting this bit high powers down the transmit digital interpolators.

It does not clear the content of the data path.

Bit 4: Power-Down DAC

Setting this bit high powers down the transmit DAC.

Bit 5, Bit 6: Power-Down PLL-A, PLL-B

Setting these bits high powers down the on-chip phase-lock

loops that generated CLK-A and CLK-B, respectively. When

powered down, these clocks are high impedance.

Bit 7: Power-Down Regulator

Setting this bit high powers down the on-chip voltage control regulator.

The AD9876 integrates two independently programmable PLLs

referred to as PLL-A and PLL-B. The outputs of the PLLs are

used to generate all the chips internal and external clock signals

from the fCLKIN signal. All Tx path clock signals are derived

from PLL-A. If fCLKIN is programmed as the ADC sampling

clock source, then the Rx port clocks are also derived from

PLL-A. Otherwise, the ADC sampling clock is PLL-B/2 and the

Rx path clocks are derived from PLL-B.

There is a restriction that the values of L and K both be equal to

4 when fCLKIN is selected as the ADC sampling clock source.

However, the best receive path performance is obtained when

fCLKIN is selected as the ADC sampling clock source and should

be used as the ADC sampling clock whenever possible.

Bit 1, 0: PLL-A Multiplier

Bits 1 and 0 determine the multiplication factor (L) for PLL-A

and the DAC sampling clock frequency, fDAC.

fDAC = L

× fCLKIN

Bit 1, 0

0, 0: L = 1

0, 1: L = 2

1, 0: L = 4

1, 1: L = 8

Bit 5 to 2: PLL-B Multiplier/Divider

Bits 5 to 2 determine the multiplication factor (M) and division

factor (N) for the PLL-B and the CLK-B frequency. For multi-

plexed 10-/12-bit data, fCLK-B = fCLKIN

× M/N. For nonmultiplexed

6-bit data, fCLK-B = (fCLKIN/2)

× M/N. All nine combinations of M

and N values are valid, yielding seven unique M/N ratios.

Bit 5,4

Bit 3,2

0, 0: M = 3

0, 0: N = 2

0, 1: M = 4

0, 1: N = 4

1, 0: M = 6

1, 0: N = 1

Bit 6: ADC Clock Source PLL-B/2

Setting Bit 6 high selects PLL-B/2 as the ADC sampling clock

source. In this mode, the Rx data and CLK-B will run at a rate

of fCLK-B. Rx SYNC will run at fCLK-B/2.

Setting Bit 6 low selects the fCLKIN signal as the ADC sampling

clock source. This mode of operation yields the best ADC

performance if an external crystal is used or a low jitter clock

source drives the OSCIN pin.

Bit 7: Tx Port Negative Edge Sampling

Setting Bit 7 high will cause the Tx Port to sample the Tx DATA

and Tx SYNC on the falling edge of CLK-A. By default, the Tx

Port sampling occurs on the rising edge of CLK-A. The timing

is shown in Figure 5.

The AD9876 receive path has a continuous time 4-pole LPF

and a 1-pole digital HPF. The 4-pole LPF has two selectable

cutoff frequencies. Additionally, the filter can be tuned around

those two cutoff frequencies. These filters can also be bypassed

to different degrees as described below.

The continuous time 4-pole low-pass filter is automatically

calibrated to one of two selectable cutoff frequencies.

The cutoff frequency fCUTOFF is described as a function of the

ADC sampling frequency fADC and can be influenced (

±30%) by

the Rx Filter Tuning Target word in Register 5.

64 64

Target

CUTOFF LOW

ADC

=×

()

158 64

Target

CUTOFF HIGH

ADC

=×

()

Bit 0: Rx LPF Bypass

Setting this bit high bypasses the 4-pole LPF. The filter is auto-

matically powered down when this bit is set.

Bit 1: Enable 1-Pole Rx LPF

The AD9876 can be configured with an additional 1-pole ~16 MHz

input filter for applications that require steeper filter roll-off or

want to use the 1-pole filter instead of the 4-pole receive low-

pass filter. The 1-pole filter is untrimmed and subject to cutoff

frequency variations of

20%.

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