REV. A

AD9876

–22–

Bit 2: Wideband Rx LPF

This bit selects the nominal cutoff frequency of the 4-pole LPF.

Setting this bit high selects a nominal cutoff frequency of 28.8 MHz.

When the wideband filter is selected, the Rx path gain is limited

to 30 dB.

Bit 3: Fast ADC Sampling

Setting this bit increases the quiescent current in the SVGA

block. This may provide some performance improvement

when the ADC sampling frequency is greater than 50 MSPS

(in 6-Bit Mode).

Bit 4: Rx Digital HPF Bypass

Setting this bit high bypasses the 1-pole digital HPF that follows

the ADC. The digital filter must be bypassed for ADC sampling

above 50 MSPS.

Bit 5: Rx Path DC Offset Correction

Writing a 1 to this bit triggers an immediate receive path offset

correction and reads back zero after the completion of the offset

correction.

Bit 6: Rx LPF Tuning in Progress

This bit indicates when the receive filter calibration is in progress.

The duration of a receive filter calibration is about 500 ms.

Writing to this bit has no effect.

Bit 7: Rx Port Negative Edge Sampling

Setting this bit high disables the automatic background receive

filter calibration. The AD9876 automatically calibrates the

receive filter on reset and every few (~2) seconds thereafter to

compensate for process and temperature variation, power sup-

ply, and long term drift. Programming a 1 to this bit disables

this function. Programming a 0 triggers an immediate first cali-

bration and enables the periodic update.

REGISTER 5—RECEIVE FILTER TUNING TARGET

See Register 4 description.

REGISTER 6—Rx PATH GAIN ADJUST

The AD9876 uses a combination of a continuous time PGA

(CPGA) and a switched capacitor PGA (SPGA) for a gain range

of –6 dB to +36 dB with a resolution of 2 dB. The Rx path gain

can be programmed over the serial interface by writing to the

Rx Path Gain Adjust Register or directly using the GAIN and

MSB aligned Tx [5:1] Bits. The register default value is 0

× 00

for the lowest gain setting (–6 dB). The register always reads

back the actual gain setting irrespective of which of the two

programming modes were used.

Table V describes the gains and how they are achieved as a

function of the Rx Path adjust bits.

Bit 5: PGA Gain Set by Register

Setting this bit high will result in the Rx Path Gain being set by

writing to the PGA Gain Control Register. Default is zero which

selects writing the gain through the Tx [5:1] pins in conjunction

with the gain pin.

Table V. PGA Programming Map

Rx Path

Rx Path

CPGA

SPGA

Gain [4:0]

Gain

Gain

Gain

0

× 00

–6

–6

0

0

× 01

–4

–6

2

0

× 02

–2

–6

4

0

× 03

0

–6

6

0

× 04

2

–6

8

0

× 05

4

–6

10

0

× 06

606

0

× 07

808

0

× 08

10

0

10

0

× 09

12

6

6

0

× 0A

14

6

8

0

× 0B

16

6

10

0

× 0C

18

12

6

0

× 0D

20

12

8

0

× 0E

22

12

10

0

× 0F

24

18

6

0

× 10

26

18

8

0

× 11

28

18

10

0

× 12*

30/30

18/24

12/6

0

× 13*

30/32

18/24

12/8

0

× 14*

30/34

18/24

12/10

0

× 15*

30/36

18/24

12/12

*When the Wideband Rx Filter Bit is set high, the Rx Path Gain is limited to

30 dB. The first of the two values in the chart refers to this mode. The second

number refers to the mode when the lower Rx LPF Cutoff Frequency is cho-

sen, or the Rx LPF Filter is bypassed.

REGISTER 7—TRANSMIT PATH SETTINGS

The AD9876 transmit path has a programmable interpolation

filter that proceeds the transmit DAC. The interpolation filter

can be programmed to operate in seven different modes. Also,

the digital interface can be programmed to operate in several

different modes. These modes are described below.

Bit 0: Transmit Port Demultiplexer Bypass

Setting Bit 0 high bypasses the input data demultiplexer. In this

mode, consecutive nibbles on the Tx [5:0] pins are treated as

individual words to be sent through the Tx path. This creates a

six bit data path. The state of Tx SYNC is ignored in this mode.

Bit 2: Transmit Port Least Significant Nibble First

Setting Bit 2 high reconfigures the AD9876 for a Transmit

Mode that expects least significant nibble before the most

significant nibble.

Bit 3: Power-Down Interpolator at

Tx QUIET Pin Low

Setting Bit 3 high enables the

Tx QUIET pin to shut off the

DAC output. If the bit is set to 1, then pulling the

Tx QUIET

pin low will power down the interpolator filters. In most appli-

cations, the interpolator filter will need to be flushed with 0s

before or after being powered down.