AD9876BST datasheet(23/24 Pages) AD

23 / 24 page

REV. A

AD9876

–23–

Bit 4 to Bit 7: Interpolation Filter Select

Bits 4 to 7 define the interpolation filter characteristics and

interpolation rate.

Bits 7:4;

× 2; Interpolation Bypass

× 0; see TPC 1. 4× Interpolation, LPF

× 1; see TPC 2. 2× Interpolation, LPF

× 4; see TPC 3. 4× Interpolation, BPF, Adjacent Image

× 5; see TPC 4. 2× Interpolation, BPF, Adjacent Image

× 8; see TPC 5. 4× Interpolation, BPF, Lower Image

× C; see TPC 6. 4× Interpolation, BPF, Upper Image

The interpolation factor has a direct influence on the CLK-A

output frequency. When the transmit input data multiplexer is

enabled (10-/12-Bit Mode):

CLK A

DAC

−

=×

where K is the interpolation factor. When the transmit input data

multiplexer is disabled (5-/6-Bit Mode):

CLK A

DAC

−

where K is the interpolation factor.

SETTINGS

Bit 0: Rx Port Multiplexer Bypass

Setting this bit high bypasses the Rx Port output multiplexer.

This will output only the 6 MSBs of the ADC word. This mode

enables ADC sampling rates above 55 MSPS.

Bit 2: Rx Port LS Nibble First

Reconfigures the AD9876 for a Receive Mode that expects less

significant bits before the most significant bits.

Bit 3: Three-State Rx Port

This bit sets the receive output Rx [5:0] into a high impedance

Three-State Mode. It allows for sharing the bus with other devices.

Bit 4, Bit 5: Disable CLK-A, Disable CLK-B

Setting Bit 4 or Bit 5 stops CLK-A or CLK-B, respectively,

from toggling. The output is held low. Setting Bit 4 or Bit 5

fixes CLK-A or CLK-B to a low output level, respectively.

Bit 6: Invert CLK-A

Setting Bit 6 high inverts the CLK-A output signal.

Bit 7: Invert CLK-B

Setting this bit high inverts the CLK-B output signal. This effec-

tively changes the timing of the Rx [5:0] and Rx SYNC signals

from rising edge triggered to falling edge triggered with respect

to the CLK-B signal.

This register stores the die revision of the chip. It is a Read-

Only Register.

PCB DESIGN CONSIDERATIONS

Although the AD9876 is a mixed-signal device, the part should

be treated as an analog component. The digital circuitry on-chip

has been specially designed to minimize the impact that the

digital switching noise will have on the operation of the analog

circuits. Following the power, grounding and layout recommen-

dations in this section will help you get the best performance

from the MxFE.

Component Placement

If the three following guidelines of component placement are

followed, chances for getting the best performance from the

MxFE are greatly increased. First, manage the path of return

currents flowing in the ground plane so that high frequency

switching currents from the digital circuits do not flow on the

ground plane under the MxFE or analog circuits. Second, keep

noisy digital signal paths and sensitive receive signal paths as

short as possible. Third, keep digital (noise generating) and

analog (noise susceptible) circuits as far away from each other

as possible.

In order to best manage the return currents, pure digital circuits

that generate high switching currents should be closest to the

power supply entry. This will keep the highest frequency return

current paths short and prevent them from traveling over the

sensitive MxFE and analog portions of the ground plane. Also,

these circuits should be generously bypassed at each device

which will further reduce the high frequency ground currents.

The MxFE should be placed adjacent to the digital circuits,

such that the ground return currents from the digital sections

will not flow in the ground plane under the MxFE. The analog

circuits should be placed furthest from the power supply.

The AD9876 has several pins that are used to decouple sensitive

internal nodes. These pins are REFIO, REFB, and REFT. The

decoupling capacitors connected to these points should have

low ESR and ESL. These capacitors should be placed as close

to the MxFE as possible and be connected directly to the analog

ground plane.

The resistor connected to the FSADJ pin should also be placed close

to the device and connected directly to the analog ground plane.

Power Planes and Decoupling

The AD9876 evaluation board demonstrates a good power

supply distribution and decoupling strategy. The board has four

layers: two signal layers, one ground plane, and one power plane.

The power plane is split into a 3VDD section used for the 3 V

digital logic circuits, a DVDD section used to supply the digital

supply pins of the AD9876, an AVDD section used to supply

the analog supply pins of the AD9876/AD9875, and a VANLG

section that supplies the higher voltage analog components on

the board. The 3VDD section will typically have the highest

frequency currents on the power plane and should be kept the

furthest from the MxFE and analog sections of the board. The

DVDD portion of the plane brings the current used to power

the digital portion of the MxFE to the device. This should be

treated similarly to the 3VDD power plane and be kept from

going underneath the MxFE or analog components. The MxFE

should largely sit on the AVDD portion of the power plane.

The AVDD and DVDD power planes may be fed from the same

low noise voltage source; however, they should be decoupled

from each other to prevent the noise generated in the DVDD

portion of the MxFE from corrupting the AVDD supply. This

can be done by using ferrite beads between the voltage source and

DVDD and between the source and the AVDD. Both DVDD

and AVDD should have a low ESR, bulk decoupling capacitor

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