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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9876 датащи(PDF) 20 Page - Analog Devices |
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AD9876 датащи(HTML) 20 Page - Analog Devices |
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20 / 24 page  REV. A AD9876 –20– the first address to be accessed. The AD9876 will automatically increment the address for each successive byte required for the multibyte communication cycle. Figures 10a and 10b show how the serial port words are built for each of these modes. SENABLE SCLK SDATA R/W I6(N) I5(N) I3 I4 I2 I1 I0 D7N D6N D20 D10 D00 INSTRUCTION CYCLE DATA TRANSFER CYCLE Figure 10a. Serial Register Interface Timing MSB-First SENABLE SCLK SDATA I0 I6(N) I5(N) I3 I4 I2 I1 R/W D7N D6N D20 D10 D00 INSTRUCTION CYCLE DATA TRANSFER CYCLE Figure 10b. Serial Register Interface Timing LSB-First Notes on Serial Port Operation The serial port is disabled and all registers are set to their default values during a hardware reset. During a software reset, all registers except Register 0 are set to their default values. Regis- ter 0 will remain at the last value sent, with the exception that the Software Reset Bit will be set to 0. The serial port is operated by an internal state machine and is dependent on the number of SCLK cycles since the last time SENABLE went active. On every eighth rising edge of SCLK, a byte is transferred over the SPI. During a multibyte write cycle, this means the registers of the AD9876 are not simultaneously updated but occur sequentially. For this reason, it is recom- mended that single byte transfers be used when changing the SPI configuration or performing a software reset. Table IV. Register Layout Address Default (hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (hex) Comments 0 SPI Software 0 × 00 Read/Write LSB First Reset 1 Power- Power- Power- Power- Power- Power- Power- Power- 0 × 00 Read/Write Down Down Down Down Down Down Down Down PWR DN Regulator PLL-B PLL-A DAC Interpolator Rx ADC and Rx LPF and Pin Low Reference FPGA CPGA 2 Power- Power- Power- Power- Power- Power- Power- Power- 0 × 9F Read/Write Down Down Down Down Down Down Down Down PWR DN Regulator PLL-B PLL-A DAC Interpolator Rx ADC and Rx LPF and Pin High Reference FPGA CPGA 3Tx Port ADC Clock PLL-B PLL-B PLL-A 0 × 02 Read/Write Negative Source ( ×M) Multiplier ( N) Divider ( ×M) Multiplier EdgePLL-B/2 <5:4> <3:3> <1:0> Sampling 4Rx Port Rx LPF Rx Path Rx Digital Fast ADC Wideband Enable Rx LPF 0 × 01 Read/Write Negative Tuning DC Offset HPF Sampling Rx LPF 1-Pole Bypass Edge In Progress Correction Bypass Rx LPF Sampling (Read-Only) 5Rx LPF fc Adjust <7:0> 0 × 80 Read/Write 6 PGA Rx Path Gain Adjust <4:0> 0 × 00 Read/Write Gain Set by Register 7Interpolation Filter Select Power-Down Tx Port Tx Port 0 × 00 Read/Write <3:0> Interpolator LS Nibble Demultiplexer at First Bypass Tx QUIET Pin Low 8 Invert Invert Disable Disable Three-State Rx Port Rx Port 0 × 00 Read/Write CLK-B CLK-A CLK-B CLK-A Rx Port LS Nibble Multiplexer First Bypass FDie Revision Number <3:0> Read- Only |
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