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AD9782 датащи(PDF) 21 Page - Analog Devices

номер детали AD9782
подробное описание детали  12-Bit, 200 MSPS/500 MSPS TxDAC with 2 x /4 x /8 x Interpolation and Signal Processing
PDF  52 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD9782 датащи(HTML) 21 Page - Analog Devices

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Preliminary Technical Data
AD9782
Rev. PrC | Page 21 of 52
Table 15.
PLL(04)
Bit
Direction
Default
Description
PLLON
7
I
0
0: PLL off
1: PLL on
PLLMULTI[1:0]
[6:5]
I
00
PLL MULTIPLY FACTOR
00: ×2
00: ×4
00: ×8
00: ×16
PLLDIV[1:0]
[4:3]
I
00
PLLMULT rate divide factor
00:/1
00:/2
00:/4
00:/8
PLLAZBW[1:0]
[2:1]
I
00
PLL Autozero settling bandwidth as fraction of CLK ±rate
00: /8 (lowest)
01: /4
10: /2 (highest)
PLOCKEXT
0
I
0
0: With PLL on, DATACLK/PLL_LOCK pin configured for DATACLK input/output
1: With PLL on, DATACLK/PLL_LOCK pin configured for output of PLLLOCK
Table 16.
DCLKCRC(05)
Bit
Direction
Default
Description
DATADJ[3:0]
[7:4]
I
0000
DATACLK offset. Twos complement respresentation
0111: +7
:
0000: 0
:
1000: -8
MODSYNC
3
I
00
0: With PLOCKEXT off, channel data rate clock synchronizer mode
1: With PLOCKEXT off, state machine clock synchronizer mode
fS/8
fS/4
fS/2
000
1
1
1
001
1/√2
0
–1
010
0
–1
1
011
–1/√2
0
–1
100
–1
1
1
101
–1/√2
0
–1
110
0
–1
1
MODADJ[2:0]
[2:0]
I
000
111
1/√2
0
–1
Modulator coefficient offset
Table 17.
VERSION(0D)
Bit
Direction
Default
Description
VERSION[3:0]
[3:0]
O
–
Hardware version identifier



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