VSC7182 datasheet(13/18 Pages) VITESSE

13 / 18 page

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7182

Quad Transceiver

for Gigabit Ethernet and Fibre Channel

G52307-0, Rev 2.2

Page 13

10/10/00

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

R5, P5

R7, P7

P11, R11

P13, R13

TA+, TA-

TB+, TB-

TC+, TC-

TD+, TD-

OUTPUT - Differential PECL (AC-coupling recommended):

These pins output the serialized transmit data for Channel x when PLUP is LOW.

When PLUP is HIGH, TXi+ is HIGH and TXi- is LOW.

D1, D2, E3

E4, C1, C2

C3, B1, B2

RA0, RA1, RA2

RA3, RA4, RA5

RA6, RA7, RA8

RA9

OUTPUT - TTL: 10-Bit Receive Bus for Channel A. Parallel data on this bus is

synchronous to RCA0 and RCA1. RA0 is the first bit received.

A6, B6, C6

D6, A7, D7

A8, B8, C8

RB0, RB1, RB2

RB3, RB4, RB5

RB6, RB7, RB8

RB9

OUTPUT - TTL: 10-Bit Receive Bus for Channel B. Parallel data on this bus is

synchronous to RCB0 and RCB1. RB0 is the first bit received.

B11, A12, B12

C12, D12, B13

C13, D13, A14

B14

RC0, RC1, RC2

RC3, RC4, RC5

RC6, RC7, RC8

RC9

OUTPUT - TTL: 10-Bit Receive Bus for Channel C. Parallel data on this bus is

synchronous to RCC0 and RCC1. RC0 is the first bit received.

C17, D14, D15

D16, D17, E16

E17, F14, F15

F16

RD0, RD1, RD2

RD3, RD4, RD5

RD6, RD7, RD8

RD9

OUTPUT - TTL: 10-Bit Receive Bus for Channel D. Parallel data on this bus is

synchronous to RCD0 and RCD1. RD0 is the first bit received.

RCM

INPUT - TTL: Recovered Clock MODE Control. When LOW, RCi0/RCi1 is 1/20th of

the incoming baud rate. When HIGH, RCi0/RCi1 is 1/10th the incoming baud rate.

RCA0

RCA1

OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel A

at 1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW).

Synchronous to the RA(0:9) and SYNCA bus.

RCB0

RCB1

OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel B at

1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous

to the RB(0:9) and SYNCB bus.

C10

D10

RCC0

RCC1

OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel C at

1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW). Synchronous

to the RC(0:9) and SYNCC bus.

B16

B17

RCD0

RCD1

OUTPUT - Complementary TTL: Recovered Complementary Clocks for Channel D

at 1/10th the Incoming Baud Rate (RCM=HIGH) or 1/20th (RCM=LOW).

Synchronous to the RD(0:9) and SYNCD bus.

U4, U3

U7, U6

U11, U10

U14, U13

RA+, RA-

RB+, RB-

RC+, RC-

RD+, RD-

INPUT - Differential PECL (AC-coupling recommended): Serial Receive Data Inputs

for Channel x. These are selected when PLUP is LOW (internally biased to VDD/2).

Name

Description

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