LTC4258 datasheet(23/28 Pages) LINER

23 / 28 page

LTC4258

4258p

it is sending its address, it monitors the SDAIN pin to see

if another device is sending an address at the same time

using standard I2C bus arbitration. If the LTC4258 is

sending a 1 and reads a 0 on the SDAIN pin on the rising

edge of SCL, it assumes another device with a lower

address is sending and the LTC4258 immediately aborts

its transfer and waits for the next ARA cycle to try again.

If transfer is successfully completed, the LTC4258 will

stop pulling down the INT pin. When the INT pin is released

in this way or if a 1 is written into the Clear Interrupt pin bit

(bit 6 of register 1Ah), the condition causing the LTC4258

to pull the INT pin down must be removed before the

LTC4258 will be able to pull INT down again. This can be

done by reading and clearing the event registers or by

writing a 1 into the Clear All Interrupts bit (bit 7 of register

1Ah). The state of the INT pin can only change between I2C

transactions, so an interrupt is cleared or new interrupts

are generated after a transaction completes and before

new I2C bus communication commences. Periodic polling

of the alert response address can be used instead of the

INT pin if desired. If any device acknowledges the alert

response address, then the INT line, if connected, would

have been low.

System Software Strategy

Control of the LTC4258 hinges on one decision, the

LTC4258’s operating mode. The three choices are de-

scribed under Operating Modes. In Auto mode the LTC4258

can operate autonomously without direction from a host

controller. Because LTC4258s running in Auto mode will

power every valid PD connected to them, the PSE must

have 15.4W/port available. To reduce the power require-

ments of the –48V supply, PSE systems can track power

usage, only turning on ports when sufficient power is

available. The IEEE describes this as a power allocation

algorithm and places two limitations: the PSE shall not

power a PD unless it can supply the guaranteed power for

that PD’s class (see Table 2) and power allocation may not

APPLICATIO S I FOR ATIO

be based solely on a history of each PD’s power consump-

tion. In order for a PSE to implement power allocation, the

PSE’s processor/controller must control whether ports

are powered—the LTC4258 cannot be allowed to operate

in Auto mode. Semiauto mode fits the bill as the LTC4258

automatically detects and classifies PDs, then makes this

information available to the host controller, which de-

cides to apply power or not. Operating the LTC4258 in

Manual mode also lets the controller decide whether to

power the ports but the controller must also control

detection and classification. If the host controller oper-

ates near the limit of its computing resources, it may not

be able to guide a Manual mode LTC4258 through detect,

class and port turn-on in less than the IEEE mandated

maximum of 950ms.

In a typical PSE, the LTC4258s will operate in Semiauto

mode as this allows the controller to decide to power a

port without unduly burdening the controller. With an

interrupt mask of F4h, the LTC4258 will signal to the host

after it has successfully detected and classed a PD, at

which point the host can decide whether enough power is

available and command the LTC4258 to turn that port on.

Similarly, the LTC4258 will generate interrupts when a

port’s power is turned off. By reading the LTC4258’s

interrupt register, the host can determine if a port was

turned off due to overcurrent (tSTART or tICUT faults) or

because the PD was removed (Disconnect event). The

host then updates the amount of available power to reflect

the power no longer consumed by the disconnected PD.

Setting the MSB of the interrupt mask causes the LTC4258

to communicate fault conditions caused by failures within

the PSE, so the host does not need to poll to check that the

LTC4258s are operating properly. This interrupt driven

system architecture provides the controller with the final

say on powering ports at the same time, minimizing the

controller’s computation requirements because inter-

rupts are only generated when a PD is detected or on a

fault condition.

LTC4258 датащи(PDF) 23 Page - Linear Technology

LTC4258 датащи(HTML) 23 Page - Linear Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

датащи скачать

ссылки URL