DS3153N datasheet(20/60 Pages) DALLAS

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DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs

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SRLn

Status Register Latched

04h, 14h, 24h, 34h

Bit

Name

—

TDML

PRBSL

PBERL

RCVL

RLOLL

RLOSL

Default

—

Bit 5: Transmitter Driver Monitor Latched (TDML). This latched status bit is set to one when the TDM status bit

changes state (low to high or high to low). TDML is cleared when the host processor writes a one to it and is not set

again until TDM changes state again. When TDML is set, it can cause a hardware interrupt to occur if the TDMIE

interrupt-enable bit is set to one. The interrupt is cleared when TDML is cleared or TDMIE is set to zero.

Bit 4: PRBS Detector Output Latched (PRBSL). This latched status bit is set to one when the PRBS status bit

changes state (low to high or high to low). PRBSL is cleared when the host processor writes a one to it and is not

set again until PRBS changes state again. When PRBSL is set, it can cause a hardware interrupt to occur if the

PRBSIE interrupt-enable bit is set to one. The interrupt is cleared when PRBSL is cleared or PRBSIE is set to zero.

Bit 3: PRBS Detector Bit Error Latched (PBERL). This latched status bit is set to one when the PRBS detector is

in sync and a bit error has been detected. PBERL is cleared when the host processor writes a one to it and is not

set again until another bit error is detected. When PBERL is set, it can cause a hardware interrupt to occur if the

PBERIE interrupt-enable bit is set to one. The interrupt is cleared when PBERL is cleared or PBERIE is set to zero.

Bit 2: Receiver Code Violation Latched (RCVL). This latched status bit is set to one when the RCV status bit

goes high. RCVL is cleared when the host processor writes a one to it and is not set again until RCV goes high

again. When RCVL is set, it can cause a hardware interrupt to occur if the RCVIE interrupt-enable bit is set to one.

The interrupt is cleared when RCVL is cleared or RCVIE is set to zero.

Bit 1: Receiver Loss-of-Clock Lock Latched (RLOLL). This latched status bit is set to one when the RLOL status

bit changes state (low to high or high to low). RLOLL is cleared when the host processor writes a one to it and is

not set again until RLOL changes state again. When RLOLL is set, it can cause a hardware interrupt to occur if the

RLOLIE interrupt-enable bit is set to one. The interrupt is cleared when RLOLL is cleared or RLOLIE is set to zero.

Bit 0: Receiver Loss-of-Signal Latched (RLOSL). This latched status bit is set to one when the RLOS status bit

changes state (low to high or high to low). RLOSL is cleared when the host processor writes a one to it and is not

set again until RLOS changes state again. When RLOSL is set, it can cause a hardware interrupt to occur if the

RLOSIE interrupt-enable bit is set to one. The interrupt is cleared when RLOSL is cleared or RLOSIE is set to zero.

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