BT8376EPF datasheet(23/323 Pages) CONEXANT

23 / 323 page

Bt8370/8375/8376

1.0 Pin Descriptions

Fully Integrated T1/E1 Framer and Line Interface

1.1 Pin Assignments

N8370DSE

Conexant

1-7

Digital Receiver (RCVR)

RCKI

RX Clock Input

Line rate clock samples RPOSI and RNEGI when RLIU configured to

accept dual-rail digital data (see [RDIGI; addr 020]); otherwise, RCKI is

ignored.

RPOSI

RX Positive Rail Input

Line rate data input on falling edge of RCKI. RPOSI and RNEGI levels are

interpreted as received AMI pulses, encoded as follows:

NOTE:

The NRZ data can be input at RPOSI or RNEGI if the

other input is connected to ground.

RNEGI

RX Negative Rail

Input

Line rate data input on falling edge of RCKI. See RPOSI signal definition.

RCKO

RX Clock Output

RPLL recovered line rate clock (RXCLK) or jitter attenuated clock (JCLK)

output, based on programmed clock selection (see [JAT_CR; addr 002]).

RPOSO

RX Positive Rail

Output

Line rate data output on rising edge of RCKO. Active-high indicates receipt

of a positive AMI pulse on RTIP/RING inputs.

RNEGO

RX Negative Rail

Output

Line rate data output on rising edge of RCKO. Active-high indicates receipt

of a negative AMI pulse on RTIP/RING inputs.

RDLO

RX Data Link Output

Line rate NRZ data output from receiver on falling edge of RCKO, all data

from RLIU is represented at the RDLO pin. However, selective RDLO bit

positions are also marked by RDLCKO for external data link applications.

RDLCKO

RX Data Link Clock

Output

Gapped version of RCKO for external data link applications. RDLCKO high

clock pulse coincides with low RCKO pulse interval during selected time

slot bits, else RDLCKO low (see Figure 2-12,

Receive External Data Link

Waveforms, External Data Link).

Table 1-1. Hardware Signal Definitions (4 of 8)

Pin Label

Signal Name

I/O

Definition

RPOSI

RNEGI

RX Pulse Polarity

No pulse

Negative AMI pulse

Positive AMI pulse

Invalid

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