BT8376EPF datasheet(133/323 Pages) CONEXANT

133 / 323 page

Bt8370/8375/8376

3.0 Registers

Fully Integrated T1/E1 Framer and Line Interface

3.4 Interrupt Status Registers

N8370DSE

Conexant

3-15

3.4 Interrupt Status Registers

Unused bits indicated by a dash (—) are reserved and should be written to 0. Writing to reserved bits has no

effect.

An Interrupt Status register (ISR) bit is latched active (high) whenever its corresponding interrupt source

reports an interrupt event. The processor reads ISR to clear all latched ISR bits. If the corresponding interrupt

enable is active (high), each interrupt event forces the associated IRR bit active (high) and the INTR* output pin

active (low). Interrupt sources fall into two categories:

• Rising-edge source reports an interrupt event when status changes from inactive to active state. Unless

specifically noted otherwise, all ISR bits are rising-edge sources.

• Dual-edge source reports an interrupt event when status changes from inactive to active (rising edge),

or from active to inactive (falling edge). The processor must read the associated real-time status to

determine which edge occurred.

Interrupt events are reported in real time on the INTR* output pin if the interrupt enable is active (high).

Otherwise, the interrupt status is latched and reported according to the selected latching mode [LATCH;

addr 046] without asserting the INTR* output pin. Table 3-3 summarizes the interrupt status registers.

Table 3-3. Interrupt Status Register Summary

Bit

004

ISR7

ALARM1

005

ISR6

ALARM2

006

ISR5

ERROR

007

ISR4

COUNT

008

ISR3

TIMER

009

ISR2

DL1

00A

ISR1

DL2

00B

ISR0

PATT

SIGFRZ

ONESEC

FERR

FERR[12]

RFRAME

TMSG

TMSG(1)

TFERR

RLOF

TLOF

MERR

CRC[10]

RMF

TNEAR

TNEAR(1)

TMERR

2RLOS

—

SERR

LCV[16]

RMSYNC

TEMPTY

TEMPTY(1)

TSERR

RALOS

TLOC

CERR

FEBE[10]

RSIG

TDLERR

TDLERR(1)

TCERR

RAIS

TSHORT

JERR

BERR[12]

TFRAME

RMSG

RMSG(1)

PSYNC

RPDV

TPDV

CKERR

SEF[2]

TMF

RNEAR

RNEAR(1)

BSLIP

RYEL

LOOPUP

RSLIP

COFA[2]

TMSYNC

RFULL

RFULL(1)

—

RMYEL

LOOPDN

TSLIP

RLOF[4]

TSIG

TBOP

RBOP

—

NOTE(S):

(1) These bits are not active in the Bt8376 Device.

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