54LS114 datasheet(3/6 Pages) NSC

номер детали	54LS114

подробное описание детали	Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears

PDF	6 Pages

Scroll/Zoom	100%

производитель	NSC [National Semiconductor (TI)]

домашняя страница	http://www.national.com

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3 / 6 page

Electrical Characteristics (Continued)

Over recommended operating free air temperature range (unless otherwise noted)

Symbol

Parameter

Conditions

Min

Typ

Max

Units

(Note 1)

IIL

Low Level Input Current

VCC e Max VI e 04V Jn Kn Inputs

SD1 SD2 Inputs

CD Input

CP Input

144

IOS

Short Circuit

VCC e Max

100

Output Current

(Note 2)

ICC

Supply Current

VCC e Max VCP e 0V

Note 1

All typicals are at VCC e 5V TA e 25 C

Note 2

Not more than one output should be shorted at a time and the duration should not exceed one second

Switching Characteristics

VCC ea50V TA ea25 C (See Section 1 for Test Waveforms and Output Load)

Symbol

Parameter

RL e 2k CL e 15 pF

Units

Min

Max

fmax

Maximum Count Frequency

MHz

tPLH

Propagation Delay

tPHL

CP toQorQ

tPLH

Propagation Delay

tPHL

CD or SDntoQorQ

Truth Table

Inputs

Output

tna1

Asynchronous Inputs

LOW input to SD sets Q to HIGH level

LOW input to CD sets Q to LOW level

Clear and Set are independent of clock

Simultaneous LOW on CD and SD

makes both Q and Q HIGH

H e HIGH Voltage Level

L e LOW Voltage Level

tn e Bit time before clock pulse

tna1 e Bit time after clock pulse

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