MP7636A

2

Rev. 2.00

ORDERING INFORMATION

Package

Type

Temperature

Range

Part No.

SOIC

SOIC

–40 to +85

+2+2

MP7636AJS

+4+4

MP7636AKS

0.1

–40 to +85

0.1

INL

(LSB)

Gain Error

(% FSR)

DNL

(LSB)

*Contact factory for non-compliant military processing

PIN CONFIGURATION

20

1

11

10

2

3

4

5

6

7

15

14

13

12

17

16

8

9

19

18

DB12 (DB4)

DB13 (DB5)

DB14 (DB6)

DB15 (MSB) (DB7)

AGND

DB11 (DB3)

DB10 (DB2)

DB9 (DB1)

DB8 (DB0, LSB)

DGND

20 Pin SOIC (Jedec, 0. 300”)

S20

See Packaging Section for Package Dimensions

CS

WR1

BYTE1/BYTE2

WR2

XFER

PIN OUT DEFINITIONS

PIN NO.

NAME

DESCRIPTION

1CS

Chip Select (Active Low)

2

WR1

Write1 (Active Low)

3

AGND

Analog Ground

4

DB11

Data Input Bit 11 (MSB)

(DB3)

Data Input Bit 3

5

DB10

Data Input Bit 10

(DB2)

Data Input Bit 2

6

DB9

Data Input Bit 9

(DB1)

Data Input Bit 1

7

DB8

Data Input Bit 8

(DB0)

Data Input Bit 0 (LSB)

Reference Input Voltage

Internal Feedback

Resistor

10

DGND

Digital Ground

11

Current Output 1

12

Current Output 2

13

DB15 (MSB)

Data Input Bit 15

(DB7)

(Most Significant Bit)

Data Input Bit 7

14

DB14

Data Input Bit 14

(DB6)

Data Input Bit 6

15

DB13

Data Input Bit 13

(DB5)

Data Input Bit 5

16

DB12

Data Input Bit 12

(DB4)

Data Input Bit 4

17

XFER

Transfer Control Signal

(Active Low)

18

WR2

Write 2 (Active Low)

19

BYTE1/

Byte Sequence Control

BYTE2

20

Power Supply

PIN NO.

NAME

DESCRIPTION