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COP404C датащи(PDF) 3 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
номер детали COP404C
подробное описание детали  COP404C ROMless CMOS Microcontrollers
PDF  18 Pages
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производитель  NSC [National Semiconductor (TI)]
домашняя страница  http://www.national.com
Logo NSC - National Semiconductor (TI)

COP404C датащи(HTML) 3 Page - National Semiconductor (TI)

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COP404C
AC Electrical Characteristics 0 CsTAs70 C unless otherwise specified
Parameter
Conditions
Min
Max
Units
Instruction Cycle
VCCt
V
DC
m
s
Time tc
VlVCCt
V
DC
m
s
Operating CKI
VCCt
V
DC
MHz
Frequency
VlVCCt
V
DC
kHz
Duty Cycle Note
f e MHz
Rise Time Note
f e MHz external clock
ns
Fall Time Note
ns
Instruction Cycle
Re
k VCCe V
Time using D as a
Ce
pF
m
s
RC Oscillator Dual
Clock Input Note
INPUTS See
Fig
tSETUP
G Inputs
Tc a
m
s
SI Input
VCCt
V
m
s
IP Input
m
s
All Others
*
m
s
tHOLD
VCCt
V
m
s
VlVCCt
V
m
s
OUTPUT
PROPAGATION DELAY
VOUTe
V CLe
pF RLe K
IP
IP
A
A
SKIP
tPD tPD
VCCt
V
m
s
VlVCCt
V
m
s
ADDATA
tPD tPD
VCCt
V
ns
VlVCCt
V
m
s
ALL OTHER OUTPUTS
tPD tPD
VCCl
V
m
s
VlVCCt
V
m
s
MICROBUS TIMING
CLe
pF VCCe Vg
Read Operation
Fig
Chip select stable before RD btCSR
ns
Chip select hold time for RD btRCS
ns
RD pulse width btRR
ns
Data delay from RD btRD
ns
RD to data floating btDF Note
ns
Write Operation
Fig
Chip select stable before WR btCSW
ns
Chip select hold time for WR btWCS
ns
WR pulse width btWW
ns
Data setup time for WR btDW
ns
Data hold time for WR btWD
ns
INTR transition time from WR btWI
ns
Note 1
Supply current is measured after running for 2000 cycle times with a square-wave clock on CKI and all other pins pulled up to VCC with 20k resistors See
current drain equation on page 16
Note 2
Test conditions All inputs tied to VCC L lines in TRI-STATE mode and tied to Ground all outputs tied to Ground
Note 3
When forcing HALT current is only needed for a short time (approx 200 ns) to flip the HALT flip-flop
Note 4
This parameter is only sampled and not 100% tested Variation due to the device included
Note 5
Voltage change must be less than 01 VCC ina1ms period
Note 6
SO output sink current must be limited to keep VOL less than 02 VCC to prevent entering test mode
Note 7
MB TIN DUAL SEL10 SEL20 input levels at VCC or VSS
3



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