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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MB9B360L датащи(PDF) 82 Page - Cypress Semiconductor |
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MB9B360L датащи(HTML) 82 Page - Cypress Semiconductor |
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82 / 128 page  Document Number: 002-04930 Rev.*B Page 82 of 128 MB9B360L Series High-Speed Synchronous Serial (SPI = 0, SCINV = 1) (VCC = 2.7V to 5.5V, VSS = 0V) Parameter Symbol Pin Name Conditions VCC < 4.5 V VCC ≥ 4.5 V Unit Min Max Min Max Serial clock cycle time tSCYC SCKx Internal shift clock operation 4tCYCP - 4tCYCP - ns SCK↑→SOT delay time tSHOVI SCKx, SOTx -10 +10 -10 +10 ns SIN→SCK↓ setup time tIVSLI SCKx, SINx 14 - 12.5 - ns 12.5* SCK↓→SIN hold time tSLIXI SCKx, SINx 5 - 5 - ns Serial clock "L" pulse width tSLSH SCKx External shift clock operation 2tCYCP – 5 - 2tCYCP – 5 - ns Serial clock "H" pulse width tSHSL SCKx tCYCP + 10 - tCYCP + 10 - ns SCK↑→SOT delay time tSHOVE SCKx, SOTx - 15 - 15 ns SIN→SCK↓ setup time tIVSLE SCKx, SINx 5 - 5 - ns SCK↓→SIN hold time tSLIXE SCKx, SINx 5 - 5 - ns SCK falling time tF SCKx - 5 - 5 ns SCK rising time tR SCKx - 5 - 5 ns Notes: − The above characteristics apply to CLK synchronous mode. − tCYCP indicates the APB bus clock cycle time. About the APB bus number which UART is connected to, see 8. Block Diagram in this data sheet. − These characteristics only guarantee the following pins. − No chip select: SIN0_1, SOT0_1, SCK0_1 − Chip select: SIN6_0, SOT6_0, SCK6_0, SCS6_0 − When the external load capacitance CL = 30 pF. (For *, when CL = 10 pF) |
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