MP7613

8

Rev. 2.00

A standard

data port loads the data into the pre-selected DACS. If CS = 0,

the chip accesses digital data on the bus. Then address bits A0

to A2 select the appropriate DAC and LD1 loads the data into the

first-latch-bank.

When all 8-channels first-latch-banks are

loaded, then LD2 enables the second-latch-bank and updates

all 8-channels simultaneously. The selected DAC becomes

transparent (activity on the digital inputs appear at the analog

output) when both LD1 = LD2 = 0.

R1 = 0 resets the first-latch-bank. R2 = 0 resets the second-

latch-bank which sets the analog output to zero volts (data =

100...00), regardless of digital inputs.

0

Function

A2

A1

A0

Table 1. Octal Parallel Data Input 14-Bit DAC Truth Table

Load Latch 1 of DAC1

Load Latch 1 of DAC2

Load Latch 1 of DAC3

Load Latch 1 of DAC4

Load Latch 1 of DAC5

Load Latch 1 of DAC6

Load Latch 1 of DAC7

Load Latch 1 of DAC8

000

001

010

011

100

101

110

111

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

Load Latch 2 of DAC1

1

1

0

1

1

Read Latch 1 of DAC1

Read Latch 1 of DAC2

Read Latch 1 of DAC3

Read Latch 1 of DAC4

Read Latch 1 of DAC5

Read Latch 1 of DAC6

Read Latch 1 of DAC7

Read Latch 1 of DAC8

000

001

010

011

100

101

110

111

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

1

1

1

1

Reset Latch 1 of DAC1

Reset Latch 2 of DAC1

XXX

XXX

X

X

X

X

X

X

0

1

1

0

X

X

Note: 1: High, 0: Low, X: Don’t Care

RD

LD1

LD2

CS

R1

R2

Note: For timing information see Electrical Characteristics

Figure 4. Simplified Parallel Logic Port

3-8

Decoder

38

8

8

To first latch bank enable

To switches across the first latch

bank for readback enable

To second latch bank enable

To reset all first latch bank

To reset all second latch bank

A0 to A2

LD1

CS

RD

LD2

R1

R2

8