EZ-PD™ CCG3

Document Number: 002-03288 Rev. *J

Page 21 of 45

Figure 15 illustrates a Notebook DRP application diagram using a CCG3 device. The Type-C port can be used as a power provider

route the HighSpeed signals either to the USB chipset (during normal mode) or the DisplayPort Chipset (during Alternate Mode). The

SBU, SuperSpeed, and HighSpeed lines are routed directly from the Display Mux of the notebook to the Type-C receptacle.

Figure 15. DRP Application Diagram

CYPD3125-40LQXIT

40QFN

VDDD

17

VDDIO

18

VBUS_C_CTRL0

CC2

CC1

VBUS_DISCHARGE

30

32

3

5

SBU1

12

SBU2

I2C_SCL / P3.5

13

37

390pF

5%

X7R

2

VBUS_P_CTRL0

100



35

HOTPLUG_

DET / P3.3

19

VCCD

1uF

10V

X7R

AUX_P

AUX_N

14

11

9

MUX_I2C_

SCL/P1.2

10

39

OC

DPLUS

DMINUS

22

21

Type-C

Receptacle

CC2

CC1

Embedded

Controller

DisplayPort

Chipset

HPD

DP0/1/2/3

AUX+/-

USB

Chipset

D+/-

SS

Data Mux

SS

HS/SS/

DP/SBU

Lines

D+/-

10uF

50V

DMN3018SSD-13

DMN3018SSD-13

10 m

 1%

DC/DC

1uF

35V

X7R

1

VBUS_P_CTRL1

VBUS_C_CTRL1

29

DMN3018SSD-13

DMN3018SSD-13

Charger

390pF

5%

X7R

VCONN

6

V5V

4

VBUS

31

VBUS_P

40

VSYS

20

1uF

10V

0.1uF

10V

0.1uF

10V

0.1uF

10V

X7R

1uF

10V

0.1uF

10V

0.1uF

10V

HPD

I2C_SDA / P3.4

36

I2C_INT / P3.2

34

V3P3 and V5P0 are 3.3V and 5V

supplies coming from the motherboard.

CCG3 gate driver control configuration

needs to be appropriately set, based

on the VBUS FET type (nFET/pFET).

S

G

D

D

G

S

D

G

S

S

G

D

2.2K



2.2K



2.2K



7, 8, 15, 16, 23,

24, 25, 27, 28, 38

XRES

GND

33

26

GPIO

V3P3

VBUS

VBUS

V5P0

VINT20

VBUS_SUPPLY

VBUS

GND

DP/DN

SS

MUX_I2C_

SDA/P1.3

SCL SDA

X

X

X

X

X

10M



10M



10M



10M



VDDD

VDDD