MCP6S28 datasheet(17/43 Pages) MICROCHIP

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 2003 Microchip Technology Inc.

DS21117A-page 17

MCP6S21/2/6/8

4.2.2

RAIL-TO-RAIL INPUT

The input stage of the internal op amp uses two differ-

ential input stages in parallel; one operates at low VIN

(input voltage), while the other operates at high VIN.

With this topology, the internal inputs can operate to

0.3V past either supply rail. The input offset voltage is

measured at both VIN =VSS - 0.3V and VDD + 0.3V to

ensure proper operation.

The transition between the two input stages occurs

when VIN

≈ VDD- 1.5V. For the best distortion and gain

linearity, avoid this region of operation.

4.2.3

RAIL-TO-RAIL OUTPUT

The Maximum Output Voltage Swing is the maximum

swing possible under a particular output load. Accord-

ing to the specification table, the output can reach

within 60 mV of either supply rail when RL =10kΩ and

VREF = VDD/2. See Figure 2-21 for typical performance

under other conditions.

4.2.4

INPUT VOLTAGE AND PHASE

REVERSAL

The

amplifier family is designed with CMOS input

devices. It is designed to not exhibit phase inversion

when the input pins exceed the supply voltages.

Figure 2-34 shows an input voltage exceeding both

supplies with no resulting phase inversion.

The maximum voltage that can be applied to the input

pins (CHX) is VSS - 0.3V to VDD + 0.3V. Voltages on the

inputs that exceed this absolute maximum rating can

cause excessive current to flow in or out of the input

pins. Current beyond ±2 mA can cause possible reli-

ability problems. Applications that exceed this rating

must be externally limited with an input resistor, as

shown in Figure 4-2.

FIGURE 4-2:

RIN limits the current flow

into an input pin.

4.3

Resistor Ladder

The resistor ladder shown in Figure 4-1 (RLAD = RF +

RG) sets the gain. Placing the gain switches in series

with the inverting input reduces the parasitic capaci-

tance, distortion and gain mismatch.

RLAD is an additional load on the output of the PGA and

causes additional current draw from the supplies.

In Shutdown mode, RLAD is still attached to the OUT

and VREF pins. Thus, these pins and the internal ampli-

fier’s inverting input are all connected through RLAD

and the output is not high-Z (unlike the external op

amp).

While RLAD contributes to the output noise, its effect is

small. Refer to Figure 2-12.

4.4

Shutdown Mode

These PGAs use a software shutdown command.

When the SPI interface sends a shutdown command,

the internal op amp is shut down and its output placed

in a high-Z state.

The resistive ladder is always connected between

VREF and VOUT; even in shutdown. This means that the

output resistance will be on the order of 5 k

Ω and there

will be a path for output signals to appear at the input.

The Power-on Reset (POR) circuitry will temporarily

place the part in shutdown when activated. See

Section 5.4, “Power-On Reset”, for details.

RIN

VSS

Minimum expected VIN

()

–

2 mA

----------------------------------------------------------------------------

≥

RIN

Maximum expected VIN

() VDD

–

2 mA

-------------------------------------------------------------------------------

≥

VIN

RIN

VOUT

MCP6S2X

CHX

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