CIP3250A datasheet(22/44 Pages) MICRONAS

номер детали	CIP3250A

подробное описание детали	Component Interface Processor

PDF	44 Pages

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производитель	MICRONAS [Micronas]

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ADVANCE INFORMATION

CIP 3250A

Micronas

Table 2–10: I2C-Bus operation, continued

Sub-

Address

(decimal)

Label

Bit No.

(LSB = 0)

Typical

Operation

Value

Function

I2C registers for ACTIVE VIDEO SIGNAL

AVIINV

polarity of AVI signal

0 = active video during AVI is high (if <17>AVINT = 0)

1 = active video during AVI is low (if <17>AVINT = 0)

AVOINV

polarity of AVO signal

0 = AVO is high active

1 = AVO is low active

AVDLY

5–0

delay from AVI (active video in) to AVO to compensate CIP 3250A

processing delays (if <17>AVINT = 0)

(0...63) + 14 – <22>AVPR clocks (if <10>DL1ON=0)

(0...63) + 92 – <22>AVPR clocks (if <10>DL1ON=1)

AVPR

7–6

delay between AVO and YUV output

AVO preceedes YUV output by AVPR (0...3) clocks

AVINT

AVO (active video out)

0 = derived from AVI (active video in)

1 = generated internally (see <23>AVHSTRT, <24>AVHLEN,

<25>AVVSTRT, <26>AVVSTOP)

AVHSTRT

7–0

horizontal start of AVO after H-sync if <17>AVINT = 1

(0...255)*8 + 11 – <22>AVPR clocks (see Fig. 2–13)

AVHLEN

7–0

horizontal length of AVO if <17>AVINT = 1

(0...255)*8 clocks

AVVSTRT

7–0

vertical start of AVO if <17>AVINT = 1

(0...255)*4 lines

AVVSTOP

7–0

vertical stop of AVO if <17>AVINT = 1

(0...255)*4 lines

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