REV. B

–6–

AD7783

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

XTAL1

AD7783

REFIN(+)

REFIN(–)

AIN(+)

AIN(–)

IOUT1

IOUT2

IPIN

XTAL2

GND

MODE

DOUT/

RDY

CS

SCLK

RANGE

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

1

XTAL1

Input to the 32.768 kHz Crystal Oscillator Inverter.

2

REFIN(+)

4

AIN(+)

Analog Input. AIN(+) is the positive terminal of the fully differential analog input pair AIN(+)/AIN(–).

5

AIN(–)Analog Input. AIN(–) is the negative terminal of the fully differential analog input pair AIN(+)/AIN(–).

6

IOUT1

Output from Internal 200

mA Excitation Current Source. Either current source IEXC1 or IEXC2 can be

switched to this output using hardware control pin IPIN.

7

IOUT2

Output from Internal 200

mA Excitation Current Source. Either current source IEXC1 or IEXC2 can be

switched to this output using hardware control pin IPIN.

8

IPIN

Logic Input that Selects the Routing of the On-Chip Current Sources. When IPIN is tied to GND, IEXC1

IOUT2 and IEXC2 is routed to IOUT1.

9

RANGE

Logic Input that Configures the Input Range on the Internal PGA. With RANGE = 0, the full-scale input

range is

±160 mV; the full-scale input range equals ±2.56 V when RANGE = 1 for a 2.5 V reference.

10

SCLK

Serial Clock Input/Output for Data Transfers from the ADC. When the device is operated in master mode,

SCLK is an output with one SCLK period equal to one XTAL period. In slave mode, SCLK is generated

by an external source. In slave mode, all the data can be transmitted on a continuous train of pulses. Alter-

natively, it can be a noncontinuous clock with the information being transmitted from the AD7783 in

smaller batches of data. SCLK is Schmitt triggered (slave mode), making the interface suitable for opto-

isolated applications.

11

CS

Chip Select Input.

CS is an active low logic input used to select the AD7783. When CS is low, the PLL

establishes lock and allows the AD7783 to initiate a conversion. When

CS is high, the conversion is aborted,

DOUT and SCLK are three-stated, the AD7783 enters standby mode, and any conversion result in the

output shift register is lost.

12

DOUT/

RDY Serial Data Output/Data Ready Output. DOUT/RDY serves a dual purpose in this interface. When a conver-

sion is initiated, DOUT/

RDY goes high and remains high until the conversion is complete. DOUT/RDY will

then return low to indicate that valid data is available to be read from the device. In slave mode, this acts as

an interrupt to the processor, indicating that valid data is available. If data is not read after a conversion,

DOUT/

RDY will go high before the next update occurs. In master mode, DOUT/RDY goes low for at

least half an SCLK cycle before the device produces SCLKs. When SCLK becomes active, data is output

on the DOUT/

RDY pin. Data is output on the falling SCLK edge and is valid on the rising edge.

13

MODE

The MODE pin selects master or slave mode of operation. When MODE = 0, the AD7783 operates in

master mode; the AD7783 is configured for slave mode when MODE = 1.

14

GND

Ground Reference Point for the AD7783.

15

Supply Voltage, 3 V or 5 V Nominal.

16

XTAL2

Output from the 32.768 kHz Crystal Oscillator Inverter.