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Issue A

LANSDALE Semiconductor, Inc.

ML145406

Vin = ± 2V

3

5

7

14

12

10

89

1

16

VDD VCC

DI1

DI2

DI3

VSS GND

Tx3

Tx2

Tx1

Rout =

Vin

I

Figure 1. Power–Off Source Resistance (Drivers)

Figure 2. Switching Characteristics

Figure 3. Slew–Rate Characterization

DRIVERS

DI1–DI3

3 V

0 V

VOH

VOL

Tx1–Tx3

tPLH

tPHL

50%

tf

tr

10%

90%

RECEIVERS

Rx1–Rx3

DO1–DO3

+ 3 V

0 V

VOH

VOL

tPLH

tPHL

tf

tr

50%

DRIVERS

Tx1–Tx3

90%

50%

3 V

– 3 V

3 V

– 3 V

tSHL

tSLH

SLEW RATE (SR) =

– 3 V – (3 V)

OR

3 V – ( – 3 V)

tSLH

tSHL

10%

PIN DESCRIPTIONS

VDD

Positive Power Supply (Pin 1)

The most positive power supply pin, which is typically + 5

to +12V.

VSS

Negative Power Supply (Pin 8)

The most negative power supply pin, which is typically – 5

to –12 V.

VCC

Digital Power Supply (Pin 16)

The digital supply pin, which is connected to the logic power sup-

ply (maximum +5.5 V). VCC must be less than or equal to VDD.

GND

Ground (Pin 9)

Ground return pin is typically connected to the signal ground

pin of the EIA 232–E connector (Pin 7) as well as to the logic

power supply ground.

Rx1, Rx2, Rx3

Receive Data Input (Pins 2, 4, 6)

These are the EIA 232–E receive signal inputs whose volt-

ages can range from (VDD + 15 V) to (VSS – 15 V). A volt-

age between +3 and (VDD + 15 V) is decoded as a space and

causes the corresponding DO pin to swing to ground (0V); a

voltage between – 3 and (VDD – 15 V) is decoded as a mark

and causes the DO pin to swing up to VCC. The actual turn–on

input switch point is typically biased at 1.8 V above ground,

and includes 800mV of hysteresis for noise rejection. The

nominal input impedance is 5 kΩ. An open or grounded input

pin is interpreted as a mark, forcing the DO pin to VCC.

DO1, DO2, DO3

Data Output (Pins 11, 13, 15)

These are the receiver digital output pins, which swing from

VCC to GND. A space on the Rx pin causes DO to produce a

logic 0; a mark produces a logic 1. Each output pin is capable

of driving one LSTTL input load.

DI1, DI2, DI3

Data Input (Pins 10, 12,14)

These are the high–impedance digital input pins to the driv-

ers. TTL compatibility is accomplished by biasing the input

switchpoint at 1.4 V above GND. However, 5V CMOS compat-

ibility is maintained as well. Input voltage levels on these pins

must be between VCC and GND.

Tx1, Tx2, Tx3

Transmit Data Output(Pins 3, 5, 7)

These are the EIA 232–E transmit signal output pins, which

swing toward VDD and VSS. A logic 1 at a DI input causes the

corresponding Tx output to swing toward VSS. A logic 0 caus-

es the output to swing toward VDD (the output voltages will be

slightly less than VDD or VSS depending upon the output

load). Output slew rates are limited to a maximum of 30 V per

µs. When the ML145406 is off (VDD = VSS = VCC= GND),

the minimum output impedance is 300 Ω.