CYW43340 datasheet(13/96 Pages) CYPRESS

13 / 96 page

Document Number: 002-14943 Rev. *L

Page 13 of 96

PRELIMINARY

CYW43340

3.3 Frequency Selection

Any frequency within the ranges specified for the crystal and TCXO reference may be used. These include not only the standard

handset reference frequencies of 19.2, 19.44, 19.68, 19.8, 20, 26, 37.4, and 52 MHz, but also other frequencies in this range, with

approximately 80 Hz resolution. The CYW43340 must have the reference frequency set correctly in order for any of the UART or PCM

interfaces to function correctly, since all bit timing is derived from the reference frequency.

Note: The fractional-N synthesizer can support many reference frequencies. However, frequencies other than the default

require support to be added in the driver plus additional, extensive system testing. Contact Cypress for further details.

The reference frequency for the CYW43340 may be set in the following ways:

■ Set the xtalfreq=xxxxx parameter in the nvram.txt file (used to load the driver) to correctly match the crystal frequency.

■ Auto-detect any of the standard handset reference frequencies using an external LPO clock.

For applications such as handsets and portable smart communication devices, where the reference frequency is one of the standard

frequencies commonly used, the CYW43340 automatically detects the reference frequency and programs itself to the correct

reference frequency. In order for auto frequency detection to work correctly, the CYW43340 must have a valid and stable 32.768 kHz

LPO clock that meets the requirements listed in Table 4 on page 14 and is present during power-on reset.

Frequency tolerance over

the lifetime of the

equipment, including

temperature

Without trimming

–20

–

–20

–

ppm

Duty cycle

37.4 MHz clock

–––40

Phase Noise

(802.11b/g)

37.4 MHz clock at 10 kHz offset

––––––131

dBc/Hz

37.4 MHz clock at 100 kHz or greater

offset

––––––138

dBc/Hz

Phase Noise

(802.11a)

37.4 MHz clock at 10 kHz offset

––––––139

dBc/Hz

37.4 MHz clock at 100 kHz or greater

offset

––––––146

dBc/Hz

Phase Noise

(802.11n, 2.4 GHz)

37.4 MHz clock at 10 kHz offset

––––––136

dBc/Hz

37.4 MHz clock at 100 kHz or greater

offset

––––––143

dBc/Hz

Phase Noise

(802.11n, 5 GHz)

37.4 MHz clock at 10 kHz offset

––––––144

dBc/Hz

37.4 MHz clock at 100 kHz or greater

offset

––––––151

dBc/Hz

a. (Crystal) Use WRF_XTAL_OP and WRF_XTAL_ON, internal power to pin WRF_XTAL_VDD1P2.

b. (TCXO) See “TCXO” on page 11 for alternative connection methods.

c. For a clock reference other than 37.4 MHz, 20 × log10(f/ 37.4) dB should be added to the limits, where f = the reference clock frequency in MHz.

d. BT_TM6 should be tied low for a 52 MHz clock reference. For other frequencies, BT_TM6 should be tied high. Note that 52 MHz is not an auto-detected

frequency using the LPO clock.

e. The frequency step size is approximately 80 Hz resolution.

f. The crystal should be capable of handling a 200uW drive level from the CYW43340.

Table 3. Crystal Oscillator and External Clock – Requirements and Performance (Cont.)

Parameter

Conditions/Notes

Crystala

External Frequency

Referenceb,c

Min

Typ

Max

Min

Typ

Max

Units

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