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3D7503 датащи(PDF) 4 Page - Diodes Incorporated

номер детали 3D7503
подробное описание детали  MONOLITHIC MANCHESTER ENCODER/DECODER
PDF  5 Pages
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производитель  DIODES [Diodes Incorporated]
домашняя страница  http://www.diodes.com
Logo DIODES - Diodes Incorporated

3D7503 датащи(HTML) 4 Page - Diodes Incorporated

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3D7503
DEVICE SPECIFICATIONS
TABLE 2: ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
DC Supply Voltage
VDD
-0.3
7.0
V
Input Pin Voltage
VIN
-0.3
VDD+0.3
V
Input Pin Current
IIN
-10
10
mA
25C
Storage Temperature
TSTRG
-55
150
C
Lead Temperature
TLEAD
300
C
10 sec
TABLE 3: DC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V)
PARAMETER
SYMBOL
MIN
MAX
UNITS
NOTES
Static Supply Current*
IDD
40
mA
High Level Input Voltage
VIH
2.0
V
Low Level Input Voltage
VIL
0.8
V
High Level Input Current
IIH
1.0
µA
VIH = VDD
Low Level Input Current
IIL
1.0
µA
VIL = 0V
High Level Output Current
IOH
-4.0
mA
VDD = 4.75V
VOH = 2.4V
Low Level Output Current
IOL
4.0
mA
VDD = 4.75V
VOL = 0.4V
Output Rise & Fall Time
TR & TF
2
ns
CLD = 5 pf
*IDD(Dynamic) = 2 * CLD * VDD * F
Input Capacitance = 10 pf typical
where: CLD = Average capacitance load/pin (pf)
Output Load Capacitance (CLD) = 25 pf max
F = Input frequency (GHz)
TABLE 4: AC ELECTRICAL CHARACTERISTICS
(0C to 70C, 4.75V to 5.25V, except as noted)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Input Baud Rate (Encoder)
fBN
50
MBaud
Clock Frequency
fC
50
MHz
Data set-up to clock rising
tDS
3.5
ns
Data hold from clock rising
tDH
0
ns
TX High-Low time skew
t1H - t1L
-3.5
3.5
ns
1
TXB High-Low time skew
t2H - t2L
-2.0
2.0
ns
1
TX - TXB High/Low time skew
t1H - t2L
-3.0
3.0
ns
1
Nominal Input Baud Rate (Decoder)
fBN
5
50
MBaud
Allowed Input Baud Rate Deviation
fB
-0.15 fBN
0.15 fBN
MBaud
25C, 5.00V
Allowed Input Baud Rate Deviation
fB
-0.05 fBN
0.05 fBN
MBaud
-40C to 85C
4.75V to 5.25V
Allowed Input Baud Rate Deviation
fB
-0.03 fBN
0.03 fBN
MBaud
-55C to 125C
4.75V to 5.25V
Allowed Input Duty Cycle
42.5
50.0
57.5
%
Bit Cell Time
tc
1000/fB
ns
Input Data Edge to Clock Falling Edge
tCL
0.75 tc
ns
Clock Width Low
tCWL
500/fBN
ns
±2ns or 5%
Clock Falling Edge to Data Transition
tCD
3.0
4.0
5.0
ns
Notes: 1: Assumes a 50% duty cycle clock input
Doc #98009
DATA DELAY DEVICES, INC.
4
12/11/98
Tel: 973-773-2299
Fax: 973-773-9672
http://www.datadelay.com



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