4

LT3471

3471f

PI FU CTIO S

FB1N (Pin 1): Negative Feedback Pin for Switcher 1.

Connect resistive divider tap here. Minimize trace area at

for inverting topologies.

FB1P (Pin 2): Positive Feedback Pin for Switcher 1. Con-

connect to a resistive divider tap for inverting topologies.

of current. Do not pull this pin high. Must be locally

bypassed with

no less than 0.01µF and no more than 1µF.

A 0.1µF ceramic capacitor is recommended. Use this pin

as the positive feedback reference or connect a resistor

divider here for a smaller reference voltage.

FB2P (Pin 4): Same as FB1P but for Switcher 2.

FB2N (Pin 5): Same as FB1N but for Switcher 2.

SW2 (Pin 6): Switch Pin for Switcher 2 (Collector of

internal NPN power switch). Connect inductor/diode here

BLOCK DIAGRA

and minimize the metal trace area connected to this pin to

minimize EMI.

SHDN/SS2 (Pin 7): Shutdown and Soft-Start Pin. Tie to

1.8V or more to enable device. Ground to shut down. Soft-

start function is provided when the voltage at this pin is

ramped slowly to 1.8V with an external RC circuit.

SHDN/SS1 (Pin 9): Same as SHDN/SS2 but for Switcher 1.

Note: taking either SHDN/SS pin high will enable the part.

Each switcher is individually enabled with its respective

SHDN/SS pin.

SW1 (Pin 10): Same as SW2 but for Switcher 1.

Exposed Pad (Pin 11): Ground. Connect directly to local

ground plane. This ground plane also serves as a heat sink

for optimal thermal performance.

–

+

RQ

S

0.01Ω

SW1

DRIVER

10

FB1N

SHDN/SS1

1

9

FB1P

2

–

+

Σ

RAMP

GENERATOR

1.00V

REFERENCE

LEVEL

SHIFTER

1.2MHz

OSCILLATOR

GND

GND

Q1

A2

A1

8

3

–

+

RQ

S

0.01Ω

SW2

DRIVER

6

11

FB2N

SHDN/SS2

5

7

FB2P

4

–

+

Σ

RAMP

GENERATOR

LEVEL

SHIFTER

3471 F01

Q2

A4

A3

Figure 1. Block Diagram