W256

..........................Document #: 38-07256 Rev. *C Page 5 of 7

DDR Rising Edge Rate[4]

Measured between 20% to 80% of

output (Refer to Figure 1)

0.5

1.50

V/ns

DDR Falling Edge Rate[4]

Measured between 20% to 80% of

output (Refer to Figure 1)

0.5

1.50

V/ns

Output to Output Skew[4]

All outputs equally loaded

100

ps

Output t4o Output Skew for

SDRAM[2]

All outputs equally loaded

150

ps

SDRAM Buffer HH Prop. Delay[4] Input edge greater than 1 V/ns

5

10

ns

SDRAM Buffer LLProp. Delay[4]

Input edge greater than 1 V/ns

5

10

ns

Switching Waveforms

Parameter

Name

Test Conditions

Min.

Typ.

Max.

Unit

Duty Cycle Timing

All Outputs Rise/Fall Time

OUTPUT

3.3V

0V

0.4V

2.4V

2.4V

0.4V

Output-Output Skew

OUTPUT

OUTPUT

SDRAM Buffer HH and LL Propagation Delay

INPUT

OUTPUT

1.5V

1.5V

Notes:

4. All parameters specified with loaded outputs.

5. Duty cycle of input clock is 50%. Rising and falling edge rate is greater than 1V/ns.