SL28541BZCT datasheet(7/31 Pages) SILABS

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SL28541

........................ DOC #: SP-AP-0063 (Rev. AA) Page 7 of 31

Frequency Select Pin (FSA, FSB and FSC)

Apply the appropriate logic levels to FSA, FSB, and FSC

inputs before CKPWRGD assertion to achieve host clock

frequency selection. When the clock chip sampled HIGH on

CKPWRGD and indicates that VTT voltage is stable then FSA,

FSB, and FSC input values are sampled. This process

employs a one-shot functionality and once the CKPWRGD

sampled a valid HIGH, all other FSA, FSB, FSC, and

CKPWRGD transitions are ignored except in test mode.

Serial Data Interface

To enhance the flexibility and function of the clock synthesizer,

a two-signal serial interface is provided. Through the Serial

Data Interface, various device functions, such as individual

No Connect

VDD_CPU_IO

PWR

IO Power supply for CPU outputs.

CPU1#

O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending

on the configuration set in Byte 11 Bit3:2)

CPU1

O, DIF Differential CPU clock outputs. (Note: CPU1 is an iAMT clock in iAMT mode depending

on the configuration set in Byte 11 Bit3:2)

VSS_CPU

GND

Ground for outputs.

CPU#0

O, DIF Differential CPU clock outputs.

CPU0

O, DIF Differential CPU clock outputs.

VDD_CPU

PWR

3.3V Power supply for CPU PLL.

CKPWRGD/PD#

3.3V LVTTL input. This pin is a level sensitive strobe used to latch the FS_A, FS_B,

FS_C, FS_D, SRC5_SEL, and ITP_EN.

After CKPWRGD (active HIGH) assertion, this pin becomes a real-time input for

asserting power down (active LOW).

FSB/TEST_MODE

3.3V tolerant input for CPU frequency selection.

Selects Ref/N or Tri-state when in test mode

0 = Tri-state, 1 = Ref/N.

Refer to DC Electrical Specifications table for Vil_FS and Vih_FS specifications.

VSS_REF

GND

Ground for outputs.

XOUT

O, SE 14.318MHz Crystal output. (Float XOUT if using CLKIN)

XIN/CLKIN

14.318MHz Crystal input or 3.3V, 14.318MHz input clock signal.

VDD_REF

PWR

3.3V Power supply for outputs and also maintains SMBUS registers during

power-down.

REF0/FSC/TEST_SEL

I/O

3.3V tolerant input for CPU frequency selection/fixed 14.318MHz clock output.

Selects test mode if pulled to VIHFS_C when CKPWRGD is asserted HIGH. Refer

to DC Electrical Specifications table for VILFS_C, VIMFS_C, VIHFS_C specifications.

SMB_DATA

I/O

SMBus compatible SDATA.

SMB_CLK

SMBus compatible SCLOCK.

64 TSSOP Pin Definition (continued)

Pin No.

Name

Type

Description

Table 1. Frequency Select Pin (FSA, FSB and FSC)

FSC

FSB

FSA

CPU

SRC

PCIF/PCI

27MHz

REF

DOT96

USB

266 MHz

100 MHz

33 MHz

27 MHz

14.318 MHz

96 MHz

48 MHz

133 MHz

200 MHz

166 MHz

333 MHz

100 MHz

400 MHz

Reserved

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