AD8341

Rev. 0 | Page 18 of 20

Components

Function

Default Conditions

C2, C4, C7,

C9, C14, C1,

C3, C8, C10,

R2, R4, R5, R6

Supply Decoupling.

C2, C4, C7, C9, C14 = 0.1 µF

(Size 0603)

C1, C3, C8, C10 = 100 pF

(Size 0603)

R2, R4, R5, R6 = 0 Ω

(Size 0603)

R8, SW1

Output Disable Interface. The output stage of the AD8341 is disabled by applying a high

voltage to the DSOP pin by moving SW1 to Position B. The output stage is enabled moving

SW1 to Position A. The output disable function can also be exercised by applying an exter-

nal high or low voltage to the DSOP SMA connector with SW1 in Position A.

R8 = 10 kΩ (Size 0603)

SW1 = SPDT (Position A,

Output Enabled)

DSOP

VPS2

VPRF

CMRF

RFIN

RFIP

CMOP

CMOP

RFOM

RFOP

QFLP

CMOP

CMOP

CMRF

VPRF

IFLP

AD8341

C12

(OPEN)

C11

(OPEN)

C8

100pF

L3

1.2nH

C6

100pF

L4

1.2nH

C5

100pF

IBBM

IBBP

VS

RFIN

VP

QBBP

QBBM

L2

120nH

L1

120nH

C14

0.1

µF

C10

100pF

C9

0.1

µF

VP

C17

100pF

C18

100pF

RFOP

B

A

C1

100pF

C7

0.1

µF

R5

0

Ω

R4

0

Ω

C3

100pF

C4

0.1

µF

T1

ETC1-1-13

M/A-COM

SW1

R8

10k

Ω

R2

0

Ω

C2

0.1

µF

VP

TEST POINT

GND

TEST POINT

DSOP

VS

R14

4k

Ω

R11

2k

Ω

R15

44k

Ω

C15

0.1

µF

W4

R21

0

Ω

R19

0

Ω

W3

R20

0

Ω

R9

(OPEN)

R7

(OPEN)

C19

0.1

µF

VS

R12

4k

Ω

R10

2k

Ω

R13

44k

Ω

R6

0

Ω

C16

0.1

µF

W2

R17

0

Ω

R16

0

Ω

W1

R18

0

Ω

R1

(OPEN)

R3

(OPEN)

C20

0.1

µF

Figure 41. Evaluation Board Schematic