CY2SSTV855

......................... Document #: 38-07459 Rev. *F Page 2 of 6

Zero-delay Buffer

When used as a zero-delay buffer the CY2SSTV855 will likely

be in a nested clock tree application. For these applications

the CY2SSTV855 offers a differential clock input pair as a PLL

reference. The CY2SSTV855 then can lock onto the reference

and translate with near zero delay to low-skew outputs. For

normal operation, the external feedback differential input,

FBINT/C, is connected to the feedback output, FBOUTT/C. By

connecting the feedback output to the feedback input the

propagation delay through the device is eliminated. The PLL

works to align the output edge with the input reference edge

thus producing a near zero delay. The reference frequency

affects the static phase offset of the PLL and thus the relative

delay between the inputs and outputs.

When AVDD is strapped LOW, the PLL is turned off and

bypassed for test purposes.

Pin Definition[1, 2]

Pin

Name

I/O

Description

6CLKINT

I

True Clock Input. Low Voltage Differential True Clock Input.

7CLKINC

I

Complementary Clock Input. Low Voltage Differential Complementary Clock Input.

22

FBINC

I

Feedback Complementary Clock Input. Differential Input Connect to FBOUTC for

accessing the PLL.

23

FBINT

I

Feedback True Clock Input. Differential Input Connect to FBOUTT for accessing the

PLL.

3,12,17,26

YT(0:3)

O

True Clock Outputs. Differential Outputs.

2,13,16,27

YC(0:3)

O

Complementary Clock Outputs. Differential Outputs.

19

FBOUTT

O

Feedback True Clock Output. Differential Outputs. Connect to FBINT for normal

operation. A bypass delay capacitor at this output will control Input Reference/Output

Clocks phase relationships.

20

FBOUTC

O

Feedback Complementary Clock Output. Differential Outputs. Connect to FBINC for

normal operation. A bypass delay capacitor at this output will control Input

Reference/Output Clocks phase relationships.

24

PWRDWN

I

Control input to turn device in the power-down mode.

4,8,11,18,21,25

VDDQ

2.5V Power Supply for Output Clock Buffers.2.5V Nominal.

9AVDD

2.5V Power Supply for PLL. 2.5V Nominal.

1,5,14,15,28

GND

Ground

10

AGND

Analog Ground. 2.5V Analog Ground.

Function Table

Inputs

Outputs

PLL

AVDD

PWRDWN

CLKINT

CLKINC

YT(0:3)

YC(0:3)

FBOUTT

FBOUTC

GND

H

L

H

L

H

L

H

BYPASSED/OFF

GND

H

H

L

H

L

H

L

BYPASSED/OFF

2.5V

H

L

H

L

H

L

H

On

2.5V

H

H

L

H

L

H

L

On

2.5V

X

< 20 MHz

< 20 MHz

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Off

Notes:

1. PU = internal pull-up.

2. A bypass capacitor (0.1

F) should be placed as close as possible to each positive power pin (< 0.2”). If these bypass capacitors are not close to the pins their

high frequency filtering characteristic will be cancelled by the lead inductance of the traces.